ejensen@gorby.Sun.COM (Eric Jensen) (11/24/88)
In article <8523@wright.mips.COM> earl@wright.mips.com (Earl Killian) writes: >Condition codes are not only harmful for translation, but for >performance. 15% of instructions are conditional branches. If you >take two instructions instead of one to do this simple operation (set >the condition codes and then branch on them), you've just forced your >computer to execute 15% more instructions. This is nonsense. From "MIPS R2000 RISC Architecture" by Gerry Kane, pp. C-4 and C-5, I quote: "The R2000 provides a complete set of arithmetic comparisons against zero. (...). However, the only instructions for comparing a pair of registers are beq and bne. To perform any other arithmetic comparison on a pair of registers or between a register and an immediate value, you must use a sequence of two instructions as listed in Table C.1 or C.2." "Note that the MIPS assembly language supports all of the branch instructions listed in the Tables C.1 and C.2 by performing the equivalent two-instruction sequence. Refer to the Assembly Language Programmer's Guide for a description of these branch instructions." So the real question is what % of the instruction stream are branches that are not part of a two-instruction sequence AND the "corresponding" branch in a particular cc machine was preceded by a gratuitous setcc. The pixie output I have seen does not indicate what the "assembler" branch condition most likely was for the branch instructions. That would be interesting. Of course total cycles (rather than instructions) is the metric of interest; but the context is that MIPS slt, sltu, li, lui, b* and (for example) SPARC setcc, b* are all single cycle. Eric H. Jensen ejensen@sun.com