lim@cit-vax.Caltech.Edu (Kian-Tat Lim) (04/30/88)
I am interested in the architecture of the Alliant FX series of "minisupercomputers". Comments on the following subjects (and anything else you might have to add) are welcome: 1) A little history: why does the processor resemble a 68020 so much? (This was obviously intentional, as it is mentioned in the architecture manual). 2) How much do the vector instructions/registers really buy you? 3) How much does the parallelism of the FX/8 (and the new one -- I forget what it's called) really buy you? 4) The page table cache (1500 entries?!) looks immense to me; what are the tradeoffs here? [Naive thought based on little manual-reading: what happens on a context switch?] 5) Since compiler technology seems to be almost an integral part of "architecture" these days, how is Alliant's? References to published documents are fine, if I haven't done enough reading. Any other comments will be summarized if there is enough interest. Thanks. -- Kian-Tat Lim (ktl@wagvax.caltech.edu, GEnie: K.LIM1)