levy@cbnewsc.ATT.COM (Daniel R. Levy) (06/08/89)
Some time ago I asked on this group for information about RISC processors and their designers for a list I was compiling. I promised that I would send a copy of this list to whoever wanted it. I got so many responses (mostly send-me-the-list :-) that I have chosen to post the list here, rather than fight with a bunch of different mail paths. Anyone who saw my request should also see this. Thanks to those who did send suggestions. I got one message that listed the people who developed the AM29000 -- I guess that's not quite what I meant by designer but thanks anyhow. Here's the list: RISC I (UCBerkeley) RISC II (UCBerkeley) Stanford MIPS (Stanford) Accel (Celerity) 29300 (Advance Micro Devices) CAP (IT&T Advanced Technology Center) Clipper (Fairchild [now Intergraph]) CRISP (AT&T) Dragon (Xerox PARC) FAIM-1 (Schlumberger) MIPS (MIPS Computer Systems) Pyramid 90X (Pyramid Technology) Ridge 32 (Ridge Computers) ROMP (IBM) Spectrum (Hewlett-Packard) Transputer (INMOS) Whetstone I,II (Integrated Digital Products) MIPS-X (Stanford) SOAR (UCBerkeley) SPUR (UCBerkeley) 88000 (Motorola) MIPS R2000 (MIPS Computer Systems) MIPS R3000 (MIPS Computer Systems) 29000 (AMD) SPARC (Fujitsu, Cypress) 80960 (Intel) -- Daniel R. Levy UNIX(R) mail: att!ttbcad!levy, att!cbnewsc!levy AT&T Bell Laboratories 5555 West Touhy Avenue Any opinions expressed in the message above are Skokie, Illinois 60077 mine, and not necessarily AT&T's.
steves@ivory.SanDiego.NCR.COM (Steve Schlesinger x2150) (06/09/89)
In article <1173@cbnewsc.ATT.COM> levy@cbnewsc.ATT.COM (Daniel R. Levy) writes: >Some time ago I asked on this group for information about RISC processors and >their designers for a list I was compiling. I promised that I would send >a copy of this list to whoever wanted it. > > [ stuff deleted ] > >Here's the list: > [ many RISC's deleted ] >Accel (Celerity) The RISC in the Celerity products was designed and built by NCR - the NCR/32. Celerity added register window and floating point and other HW around the NCR/32. The last Celerity product developed an ECL version of a subset of the NCR/32. NCR has had RISC's embedded in its proprietary products as instruction set emulators since ~1976. > >-- >Daniel R. Levy UNIX(R) mail: att!ttbcad!levy, att!cbnewsc!levy >AT&T Bell Laboratories >5555 West Touhy Avenue Any opinions expressed in the message above are >Skokie, Illinois 60077 mine, and not necessarily AT&T's. :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: steve schlesinger steve.schlesinger@sandiego.ncr.com 619-485-2150 NCR - 4010, 16550 W Bernardo Dr, San Diego, CA 92127 ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
rogerk@mips.COM (Roger B.A. Klorese) (06/09/89)
In article <1447@ncr-sd.SanDiego.NCR.COM> steves@ivory.SanDiego.NCR.COM (Steve Schlesinger x2150) writes: >In article <1173@cbnewsc.ATT.COM> levy@cbnewsc.ATT.COM (Daniel R. Levy) writes: >>Accel (Celerity) > The RISC in the Celerity products was designed and built by > NCR - the NCR/32. Celerity added register window and floating > point and other HW around the NCR/32. ...but the NCR/32 is a RISC-come-lately in that it wasn't till the Celerity boys hung the register stack cache, etc, around it and ignored the 370-type added instruction set that the processor could be claimed to be any sort of general-purpose RISC. > The last Celerity product developed an ECL version of a subset > of the NCR/32. (a) Yes, the RISC subset. (b) "The last Celerity product" is on the market as the FPS-500 from FPS Computing. -- ROGER B.A. KLORESE MIPS Computer Systems, Inc. phone: +1 408 720-2939 928 E. Arques Ave. Sunnyvale, CA 94086 voicemail: +1 408 991-7802 {ames,decwrl,pyramid}!mips!rogerk rogerk@servitude.mips.COM "I want to live where it's always Saturday." -- Guadalcanal Diary
torbenm@freja.diku.dk (Torben Mogensen) (06/13/89)
levy@cbnewsc.ATT.COM (Daniel R. Levy) writes: >Some time ago I asked on this group for information about RISC processors and >their designers for a list I was compiling. >Here's the list: < list deleted > Acorn Computers RISC chips ARM2 and ARM3 (ARM = "Acorns RISC Machine) are missing from the list. ARM2 is used in the Archimedes series of microcomputers. ARM3 is a newly released esxtension of ARM2. The extensions include 4KB instruction and data cache, ability to use interleaved memory and a "swap-register-and-memory" instruction for better process switching. Torben Mogensen torbenm@diku.dk Disclaimer: I have no connection with Acorn Computers, apart from owning an Archimedes.
bauer@loligo.cc.fsu.edu (Jeff Bauer) (06/14/89)
In article <1173@cbnewsc.ATT.COM> levy@cbnewsc.ATT.COM (Daniel R. Levy) writes: >Some time ago I asked on this group for information about RISC processors and > >RISC I (UCBerkeley) >RISC II (UCBerkeley) . . >ROMP (IBM) . . Don't forget the "first" RISC, the 801 Minicomputer, as IBM'er George Radin called it in the March '82 CAN. I believe, though, that this is the predecessor to the ROMP. Since you do mention predecessors this is an important one to add. -- Jeff Bauer bauer@loligo.cc.fsu.edu Control Data Corporation (904) 644-2591 ext. 113
munir@hpfcmgw.HP.COM (Munir Mallal) (06/14/89)
> Here's the list: > ... > Spectrum (Hewlett-Packard) > ... > -- > Daniel R. Levy UNIX(R) mail: att!ttbcad!levy, att!cbnewsc!levy > AT&T Bell Laboratories > 5555 West Touhy Avenue Any opinions expressed in the message above are > Skokie, Illinois 60077 mine, and not necessarily AT&T's. > ---------- That should be HP Precision Architecture (HP-PA). Munir
mcp@ziebmef.uucp (Marc Plumb) (06/15/89)
Not to beat up on a chip I've worked on, but the Transputer is pretty much the opposite of most RISC chips. Lessee... very few registers, an instruction set designed for a naive compiler, tons of microcode, and an instruction set that's hard to pigeonhole, but is optimised for static code density and behaves a lot like it has variable-length instructions. *Everyone* has stolen *some* ideas from the RISC movement, but I don't think this appelation is justified. Whatever the marketroids say. -- -Colin Plumb
winter@doomb.prl.philips.nl (Pieter Winter) (06/16/89)
In article <1989Jun14.223902.12665@ziebmef.uucp> mcp@ziebmef.UUCP (Colin Plumb) writes: >Not to beat up on a chip I've worked on, but the Transputer is pretty >much the opposite of most RISC chips. Lessee... very few registers, >an instruction set designed for a naive compiler, tons of microcode, >and an instruction set that's hard to pigeonhole, but is optimised for >static code density and behaves a lot like it has variable-length >instructions. > >*Everyone* has stolen *some* ideas from the RISC movement, but I don't >think this appelation is justified. Whatever the marketroids say. >-- > -Colin Plumb This might be my mistake, but I was under the impression that the Transputer *does* have a RISC instruction set (few operations, and with an option of shifting bits up to 32?), and that the microcode does not only provide the user with the instructions, but also provides proces scheduling and i/o fascilities?? :-) I don't know anything about the registers, because I never actually programmed a transputer. Pieter ------------------------------------------------------------------------------- - Pieter Winter winter@doomb.prl.philips.nl - ------------------------------------------------------------------------------- - No man in his right mind...(?), left mind...(?), Ehhhh...(!), Nobody minds! - -------------------------------------------------------------------------------