[comp.arch] interrupt handling

henry@utzoo.uucp (Henry Spencer) (03/19/89)

In article <28200290@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:
>... applying RISC principles to the hardware that would be needed to do
>something like this, I often arrive at the conclusion that a 
>simple single entry point first level handler is all that is appropriate.

Note that the MIPS machines, as I recall, vector one or two crucial
things -- user-mode TLB misses in particular -- and just run everything
else through a single entry point.  If you want full vectoring, the
software can (and probably does) do it.  Why bother doing it in hardware?
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