pcg@cs.aber.ac.uk (Piercarlo Grandi) (01/08/91)
In comp.arch I had asked if anybody could explain why currently it seems much more difficult to get ECL *microprocessors* in production, and gave examples of several that looked promising and have faded into obscurity. I mentioned the ECL 88k project at DG, and I have been asked for details. Well, I have this old posting, which follows shortly. It would still be interesting to know what has happened. Is the ECL 88k stillborn? If so, why? Is the dominance of CMOS so great? From: chris@dg.dg.com (Chris Moriondo) Newsgroups: comp.arch Subject: Re: 88000 implementations: ECL vs CMOS Message-ID: <191@dg.dg.com> Date: 8 Jun 89 23:20:50 GMT Organization: Data General, Westboro, MA. In article <24535@shemp.CS.UCLA.EDU> marc@CS.UCLA.EDU (Marc Tremblay) writes: >Data General claims that the ECL implementation of the Motorola 88000 >family of processors is 100% compatible with the CMOS version >ie. 88100, 88200 (ref. Compcom Spring '89). >The partitioning of the two implementations is different and lead >to interesting decisions. For example in the ECL version, the FPU >is implemented on a separate chip (vs same chip in the CMOS version). >Being on a separate chip, the latency of accessing the register >file located on the integer unit became too long so DG apparently >decided to put a "copy" of the 5-port register file on the FPU as well. >In the CMOS implementation there is a single register file shared >by the integer unit and the Special Function Unit 1 (FPU). I can say a little about this. I am the manager of the group which is designing the Integer and Floating Point chips. Unfortunately I can't say a whole lot more than is already in the COMPCON paper. The ECL implementation is fully compatible architecturally with the existing CMOS implementation. The Binary Compatibility Standard requires this, at least for user mode. We didn't just give the FPU its own copy of the register file because of latency, the bandwidth requirement is also severe. Moving (up to) 192 bits of operands and results back and forth for each FP op isn't very attractive. >This leads to the following question: >How is consistency maintained between the two register files? >In the ECL implementation are writes copied between the two register files? >If so, it must generate a lot of traffic between the two chips. >Notice that the consistency has to be maintained in hardware since >the two implementations are object code compatible. Consistency is maintained in hardware. There is a dedicated data bus connecting the chips which carries the result (if any) of every instruction. Needless to say, this bus is pretty fully utilized. The scoreboard logic provides the required mechanism for interlocking instruction issue with the result transfers. A certain amount of trickiness is involved to avoid unnecessary stalls. Chris Moriondo Principal Hardware Engineer High-End Systems Development Data General Corporation usual disclaimers apply, void where prohibited, your mips may vary... -- Piercarlo Grandi | ARPA: pcg%uk.ac.aber.cs@nsfnet-relay.ac.uk Dept of CS, UCW Aberystwyth | UUCP: ...!mcsun!ukc!aber-cs!pcg Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk
davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) (01/10/91)
In article <PCG.91Jan7200131@odin.cs.aber.ac.uk> pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: | | In comp.arch I had asked if anybody could explain why currently it seems | much more difficult to get ECL *microprocessors* in production, and gave | examples of several that looked promising and have faded into obscurity. Let me say a few things about this... there are a lot more problems packaging ECL relative to CMOS. That is, ECL tends to be high power and needs to be physically larger in most cases to keep temperatures under control. Larger means longer delays so design rules all change. Market demand for a high power chip(set) is low unless the performance is really excellent. And there's the second part, the CMOS just keeps getting faster. People keep saying that the cutoff on CMOS is so many MHz or size no smaller than so many microns, and the designers keep proving those aren't the limits. Seems to me HP had some CMOS FIFO's or something last year that ran at a few GHz. And several people have told me of CMOS with "4000 angstrom design rules." What is holding ECL back, then, is a combination of things which limit the instances in which it's cost effective. If you want a faster version of an existing processor, wait a year and the original vendor will sell you one, still in CMOS, smaller, faster, lower power, and cheaper per MIP. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) VMS is a text-only adventure game. If you win you can use unix.