lan_csse@netrix.nac.dec.com (CSSE LAN Test Account) (05/02/91)
I'm posting this for a friend who was having trouble posting it at
his site. Please don't send replies to me; post your reply or send
email to the address:
gary@clipper.ingr.com
O o
X
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The other day I had a short discussion about 3 address verses 2
address architectures. The discussion went something like this.
Me> What do you think about 3 address architectures.
Him> I think they are a bad idea if you have a small number of
registers because they increase register pressure.
Me> That's not true. For every 2 address sequence there is an
equivalent 3 address sequence. You simply use the destination
address of the two address instructions as both a source and
the destination address. Hence the sequences are equivalent in
register usage. Furthermore a 3 address sequence would allow
removal of any register-to-register copies required to preserve
the value of the the destination register. Hence the sequence is
tighter.
Him> Yeah, I see your point. But, I'd guess that the real
difference is still just in the noise. This is one of those
religious issues that everyone believes in but nobody has
proved. You don't have any hard performance numbers to back you
up do you?
Me> No.
What all this boils down to is the question does anybody out
there have any hard numbers on this? If so, what are they and
how/where did you get them. If your mail bounces please post
the information. I will post a summary to the net. Please no
SWAGs or back of the envelope calculations on this. I can make
as wild a guess as the next guy.
*-------------------------*
| Gary Oblock | I apologize to those few people
| Intergraph Corp. | who saw this posting before. The
| Advanced Processor Div. | news software didn't let it out
| 2400 Geng Road | to the real world.
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| gary@clipper.ingr.com |
*-------------------------*
------- End of Forwarded Messagelewine@cheshirecat.webo.dg.com (Donald Lewine) (05/03/91)
In article <22476@shlump.nac.dec.com>, lan_csse@netrix.nac.dec.com (CSSE LAN Test Account) writes: |> |> What all this boils down to is the question does anybody out |> there have any hard numbers on this? If so, what are they and |> how/where did you get them. If your mail bounces please post |> the information. I will post a summary to the net. Please no |> SWAGs or back of the envelope calculations on this. I can make |> as wild a guess as the next guy. |> When I was a DEC, we did extensive measurements as part of doing the VAX architecture. I don't have the numbers handy (it has been 16 years), however, the answer was: Do both. Assuming that a two address instruction is smaller and faster than a three address instruction, there are a large number of cases where space and cycles can be saved by including both options. -------------------------------------------------------------------- Donald A. Lewine (508) 870-9008 Voice Data General Corporation (508) 366-0750 FAX 4400 Computer Drive. MS D112A Westboro, MA 01580 U.S.A. uucp: uunet!dg!lewine Internet: lewine@cheshirecat.webo.dg.com
spot@CS.CMU.EDU (Scott Draves) (05/06/91)
In article <1991May3.142835.9196@webo.dg.com> lewine@cheshirecat.webo.dg.com (Donald Lewine) writes:
... the answer was: Do both.
Assuming that a two address instruction is smaller and faster than
a three address instruction, there are a large number of cases where
space and cycles can be saved by including both options.
well, on modern machines all instructions are the same size, and doubt
very much that using 2-address ops would save you enough that you
could increase the clock rate (it certainly won't save you cycle
count).
As far as i can tell, on a typical RISC machine, the biggest (only?)
advantage to 2-address ops is it saves you instruction bits.
what if you made a machine with two sorts of every op: one that was
2-address, and one that was 3-address. The two address ones could
access only part of the register file.
--
christianity is stupid
Scott Draves communism is good
spot@cs.cmu.edu give upjesup@cbmvax.commodore.com (Randell Jesup) (05/07/91)
In article <SPOT.91May5235753@WOOZLE.GRAPHICS.CS.CMU.EDU> spot@CS.CMU.EDU (Scott Draves) writes: >As far as i can tell, on a typical RISC machine, the biggest (only?) >advantage to 2-address ops is it saves you instruction bits. The RPM-40 did this in order to get 16 bit instructions. >what if you made a machine with two sorts of every op: one that was >2-address, and one that was 3-address. The two address ones could >access only part of the register file. From experience, that can make compiler/backend writing a nightmare. The other win from a 2-address architecture (or rather a restated win) is that you can directly address ~1.5 times as many bits of registers in the same length instruction. For example, if you can address 16 registers in a 3-address architecture, you can address 64 registers in a two-address architecture. Interesting tradeoff - occasional extra instruction versus more spills. The weighting of the tradeoff will probably depend on the type of code being dealt with and the cost of memory accesses (for the spills). Lots more regs may cause you to change other things like subroutine interfaces. -- Randell Jesup, Keeper of AmigaDos, Commodore Engineering. {uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.commodore.com BIX: rjesup Disclaimer: Nothing I say is anything other than my personal opinion. Thus spake the Master Ninjei: "To program a million-line operating system is easy, to change a man's temperament is more difficult." (From "The Zen of Programming") ;-)
pkl@ee.mu.OZ.AU (Peter LAWREY) (05/17/91)
In article <21296@cbmvax.commodore.com> jesup@cbmvax.commodore.com (Randell Jesup) writes: >In article <SPOT.91May5235753@WOOZLE.GRAPHICS.CS.CMU.EDU> spot@CS.CMU.EDU (Scott Draves) writes: >>As far as i can tell, on a typical RISC machine, the biggest (only?) >>advantage to 2-address ops is it saves you instruction bits. > > The RPM-40 did this in order to get 16 bit instructions. > >>what if you made a machine with two sorts of every op: one that was >>2-address, and one that was 3-address. The two address ones could >>access only part of the register file. Why not use a mixed system? Ie Four registers in a 32-bit instruction which allows two formats eg. (Where R0 is always 0). A opcode dest1,src1,dest2,src2 : This allows a virtual 2 16-bit instructions opcode dest ,src1,R0 ,src2 : Acts as a 32-bit 3 operand instruction. This does however put a server restiction on the number and size of opcodes. However most of the common arithmetic opcodes can be covered. eg add,move,cmp. Even with 4 operands of 5 bits each this leaves 12 bits for the opcode (and space for other formats).