fritz@cit-vlsi.Caltech.Edu (fritz nordby) (10/23/88)
There's been some sketchy information floating around here regarding the relative speeds of CMOS and ECL, and I thought I'd throw in some information from the point of view of someone who's done a bit of CMOS circuit design. The speed/size characteristics of MOS circuits have been known for quite a while. The basic ideas were published in the early 70's (1972, I think) by Carver Mead here at Caltech. The basic question is: What happens to a MOS circuit when you scale all the dimensions by a multiplicative factor, A? Quantity Before After ======== ====== ===== length l l*A area a a*(A^2) resistance r r/A capacitance c c*A wire time const. t t voltage v v*A electric field e e transit time tau tau*A capac. energy c*v^2/2 (...)*A^3 power energy/tau (...)*A^2 power density power/a power/a The interesting characteristics of this table are: 1) speed goes up linearly 2) power goes down quadratically 3) speed-power product goes down cubically 4) power density stays the same. (Note: in the 70's and the early 80's, voltages were kept constant -- I mean, we all use +5 & ground for logic levels, right? -- so the electric fields were scaling up like e/A. For a while, that actually decreased transit times quadratically (tau*(A^2)), but not any more: electrons are velocity saturating, so even with increasing electric fields, tau is only going down linearly, and keeping the large power supplies (and believe me, 5V is huge) doesn't do anything but waste power.) So what does this all mean? Well, the transit time of a transistor is something like the fundamental time constant of the system: it's the time it takes a transistor to turn on another transistor of the same size. (Well, that's a gross simplification, but so's everything else I'm saying here.) Anyway, for technologies that aren't too old (~1985?), tau is somewhere in the 10's of picoseconds (depending on just what tau you're talking about). In the forseeable future (the next decade or so), you can expect tau to go down by another factor of 4 to 6, to somewhere around 10pS (roughly ... VERY roughly). Oh, yes, I almost forgot, dumping this stuff in liquid nitrogen does increase mobilities, so these beasties do get faster that way, too. I don't remember off the top of my head what the factor is, though, but it is quite a significant effect (factor of 2 or 5 or something like that? I'll have to dig up a copy of Sze and check. Don?). So what about ECL? Well, the same scaling rules apply to bipolar transistors, more or less, except that the critical dimension in those devices is the base width (as opposed to gate length for MOS devices). MOS gates are horizontal, which means that their size is limited by the resolution of your lithographic technique; bipolar bases are vertically oriented (the transistor is a stacked structure), so the base width is actually the base depth, and its dimension is limited by the resolution of your implant diffusion mechanism ... i.e., by how accurately you can use a stopwatch. Needless to say, the latter is easier than the former, so people have been making VERY fast bipolar devices for quite some time now, while fast MOS devices are much more recent. MOS technology is catching up, though: witness the speeds of the various 74HC series parts. So what all this adds up to is: CMOS is not slow. (The reason that old CMOS parts are slow can be seen from the scaling rules I gave above: the gates were 20 times longer, and the electric fields were (with a little bit of fudging to correct for velocity saturation effects) 10 times lower -- hence the transistors were 200 times slower.) (Another side to this is the character of the power dissipation of CMOS circuits: something which seems nice at first, but it turns on you. In fact, it's not nice at all, and it's a good reason to use BiCMOS processes: that way, you can use better drivers to export signals, and you can avoid the dreaded ringing ground line ... I mean, why do you think that TI wanted to change pin-outs for the 74HC parts? Yes, Virginia, there ARE inductors!) (Yet another side of this is the fact that wire delays are becoming larger and larger compared with device delays, so no, your chips won't be 4-6 times faster when devices are 4-6 times faster, they'll be about 2-3 times faster. Unless someone comes up with a way to use high Tc superconductors for interconnect, in which case the chips will be 10-20 times faster!) Fritz Nordby. fritz@vlsi.caltech.edu cit-vax!cit-vlsi!fritz