peter@ficc.uu.net (Peter da Silva) (10/19/88)
I have noticed one very interesting thing about RISCs lately... they are getting quite sophisticated instruction sets. 3-address operations and addressing modes aren't what I used to associate with RIS, but if you look at them they turn out to be refinements of older RISCs. What's happening, of course, is that the chips are so much faster than any sort of affordable RAM that it's worthwhile to put more into the instructions. The speed of the system as a whole goes up, since the chip can still handle all three register references in one external clock. No point in fetching instructions any faster than that... I don't know whether this will end up with a one-instruction-per-cycle 68000, before memory/cache technology catches up, but it's always interesting to watch the wheel turn. -- Peter da Silva `-_-' Ferranti International Controls Corporation. "Have you hugged U your wolf today?" peter@ficc.uu.net Disclaimer: I accept full responsibility for my own actions... but NOT until I've had my first cup of coffee.
krish@jetsun.WEITEK.COM (Krishnan Sridhar) (10/20/88)
In article <1945@ficc.uu.net>, peter@ficc.uu.net (Peter da Silva) writes: > I have noticed one very interesting thing about RISCs lately... they are > getting quite sophisticated instruction sets. 3-address operations and > addressing modes aren't what I used to associate with RIS, but if you look > at them they turn out to be refinements of older RISCs. > Yes. In fact, I would even go as far as saying that today's CISC is tomorrow's RISC (as somebody said ... everything is relative...)! - Krish
eric@snark.UUCP (Eric S. Raymond) (10/21/88)
In article <1945@ficc.uu.net>, peter@ficc.uu.net (Peter da Silva) writes: > I have noticed one very interesting thing about RISCs lately... they are > getting quite sophisticated instruction sets. 3-address operations and > addressing modes aren't what I used to associate with RIS, but if you look > at them they turn out to be refinements of older RISCs. My understanding of RISC philosophy suggests that 3-address ops and fancy addressing modes are only regarded as *symptoms* of the RISC problem -- poor match of instructions to compiler code generator capabilities, excessive miceocode-interpretation overhead in both cycles and chip real estate. If your compiler can make effective use of three-address instructions, and you've got CAD tools smart enough to gen logic for them onto an acceptably small % of the chip area (so that you don't have to give up on more important features like a big windowed register file and on-chip MMU), then I don't see any problem with calling the result a RISC. But, then, I am only-an-egg when it comes to hardware... -- Eric S. Raymond (the mad mastermind of TMN-Netnews) UUCP: ...!{uunet,att,rutgers}!snark!eric = eric@snark.UUCP Post: 22 S. Warren Avenue, Malvern, PA 19355 Phone: (215)-296-5718
henry@utzoo.uucp (Henry Spencer) (10/25/88)
In article <1945@ficc.uu.net>, peter@ficc.uu.net (Peter da Silva) writes: > I have noticed one very interesting thing about RISCs lately... they are > getting quite sophisticated instruction sets. 3-address operations and > addressing modes aren't what I used to associate with RIS, but if you look > at them they turn out to be refinements of older RISCs. Since "RISC" has become a marketing buzzword, many things are called "RISC" that are not. Also, many people are prone to say "well, RISC is a great thing, but if our hardware doesn't do XYZ directly, it can't possibly be fast", without actually studying the matter in detail to find out whether this assertion is really true. So something that starts out as a RISC gets steadily more complicated due to the union-of-wishlists effect. Only a few outfits -- MIPS and HP come to mind -- really do their homework before deciding whether to add a feature. -- The dream *IS* alive... | Henry Spencer at U of Toronto Zoology but not at NASA. |uunet!attcan!utzoo!henry henry@zoo.toronto.edu