lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (04/30/89)
In article <23649@agate.BERKELEY.EDU> matloff@heather.ucdavis.edu (Norm Matloff) writes: >There is still a strong limitation on a chip's >number of pins, right? The area of a rectangle grows much faster >than the perimeter, and of course there are mechanical reasons why >pins can't be too small. Thus the ratio of number of I/O channels >of a chip to bits stored in the chip will probably get worse, not >better. I think that solutions are coming along nicely. It would be better if there was less satisfaction with the current techniques, since they will be condsidered low-tech in a few years. About two decades ago, IBM starting interconnecting naked chips, using thin-film metallization on the face of ceramic substrates. By now, they can put ~ 100 chips onto a single substrate. The chips are bonded face-down on solder "bumps", so bonding pads can be anywhere on a chip - even in the middle of the chip. More recently, we are seeing "silicon circuit boards". Companies like Mosaic use conventional chip bonding, but to a silicon substrate instead of to a package's lead frame. Several unconventional bonding schemes are also being tried: for example, flip-bonding onto trenched cantilevers, or traces that run down the the beveled edges of the chip. The unconventional schemes pack the chips closer, but all the schemes get metallization strides of 20 to 40 microns. At 40 microns, we can get one thousand pins on a one centimeter square chip. Then, there is the group which etches chip-sized holes in silicon wafers. They take tested chips, and "glue" them into the holes so that the chip's top is planar with the wafer. The chips (and any devices in the wafer per-se) can then be interconnected by multilayer metallization. Again, there should be no reason to keep the bonding pads at the periphery of the chips. I believe that one group proposes to build up polyimide (the major ingredient of many "medium film" schemes) until it is level with a chip's top, thus planarizing the hard way. Others are doing the multilayer interconnect first, before the chips are attached. Many of these schemes have a further win, namely that they reduce the size of the on-chip bonding pads. This is a large saving when we're talking about hundreds of pads. We are also removing the inductance (etc) of the package pins, and bringing the wafer's chips very close together. The effect on performance can be considerable. The price is mitigated by the fact that the overall system may now have a smaller circuit board with fewer layers. There is also the possibility of through-wafer electrical vias. This would allow wafers to be directly stacked. Even more interesting is the possibility of through-wafer optical interconnect. Wafers - even processed ones - are close enough to transparent and nondispersive at the interesting frequencies. A Bell Labs group has successfully etched Fresnel lenses on the face of a wafer: they made a row, on 250 micron centers. The idea is not to increase received power: the lenses were intended to reduce crosstalk. Even more exciting is the new idea of epitaxial liftoff. In the past year, three labs have reported success in simply taking the active surface right off of a chip, in full working order. The technique involves creating a layer of aluminum arsenide on top of a GaAs wafer. Eptiaxial layers are added on top, forming active devices. The aluminum layer is then etched away (there is a neat trick to this) and the active layer is just taken off. The nice, thick wafer is cleaned and used again. Recently, Seymour Cray revealed that he has been taking working GaAs chips, 25 mils (600+ microns) thick, and grinding them down to 12 mils (300+ microns). He claimed that the Cray-3 is so tightly packaged that he had to do this, in order to keep the interconnects short. Ah hum. Imagine how pleased he would be if he could get the chips down to 3 (yes, three) microns thick. One lab has applied the liftoff process to a chip of transistors: they reported that the device characteristics were unchanged. Another lab has applied the process to a chip laser, five millimeters across. Afterwards, on glass, it would still lase happily. MIT's Cleft technique is similar. One report states, "50-mm-diameter GaAs layers only 5 to 10 um thick are routinely separated, and much larger thin wafers are possible." Yes, these are single-crystal layers. The Cleft technique also works for silicon. This posting is entirely too long already. But, think! For one, we could stack chips, not as two slices of toast are stacked, but more like two sheets of paper. We should be able to test the layers, or partially test them, before adding them to the stack. Do we need any new technology to make a via that's only three microns deep? (Yes, yes, we'll need electrical isolation and so on.) Registration is interesting, not because it has to be precise (big deal, these days) but because layers like this are "sticky" - an abnormal percent of their component atoms are on the surface. Another possibility: why not treat a chip as a substrate, and drop devices (like lasers) where the bonding pads would have been? Not to mention putting a solar cell on top, and floating the works onto a heat sink. -- Don D.C.Lindsay Carnegie Mellon School of Computer Science --
chip@vector.Dallas.TX.US (Chip Rosenthal) (05/01/89)
<4852@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: >matloff@heather.ucdavis.edu > (Norm Matloff) writes: >>There is still a strong limitation on a chip's number of pins, right? >I think that solutions are coming along nicely. There are some techniques available in manufacturing now for very dense systems. The most common is "chip-on-board". There are two big problems with these techniques. The first is reliability, mainly hermiticity. A lot of work has been put into garden-variety run-of-the-mill plastic DIP packages to get them to an acceptable point. It's going to be a bit before some of these advanced techniques can stand up to the same environmental stresses. The second problem is testability. It all goes back to the controlability/observability issue. As you start stacking more and more circuitry between you and the circut under test, this becomes a nontrivial problem. -- Chip Rosenthal / chip@vector.Dallas.TX.US / Dallas Semiconductor / 214-450-5337