lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (11/17/89)
In article <AGLEW.89Nov11193300@chant.urbana.mcd.mot.com> aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) writes: >I'm a wide datapath proponent myself, but some of my contacts have >responded that so many signals simulataneously changing state at the >same time => huge instantaneous power demand. > >How much of a problem is this *really*? This is well-known as one of Seymour Cray's concerns. In the Cray-1, he was worried that standing waves could develop in the copper ground plane of a circuit board. His answer was to make a machine with power demand that was (I believe) completely independant of the data flowing through it. In the Cray-3, there is some reason to believe that the circuits will have power demand that is also independent of the clock, that is, absolutely constant rather than cyclic. CMOS isn't like that. It's asymmetric, and cares about transitions: 0=>1 takes more power than 1=>1. So, one can write worst-case programs, which generate on-chip noise (mass transitions on the wide datapath), or which generate board noise and heat (mass transitions on the address and data pins). I'm not sure what cache activity generally produces the most heat: it may depend on implementation. Another fun program is the one which puts many identical settings into a content-addressable memory such as the TLB. Sixty four registers all putting their hands up at once is enough to fratz a naively designed TLB. CMOS is wonderful, but the ECL/GaAs/BiCMOS folks talk an awful good fight about how it's a different world on the other side of 50 MHz. -- Don D.C.Lindsay Carnegie Mellon Computer Science
rpeglar@csinc.UUCP (Rob Peglar x615) (11/17/89)
In article <7000@pt.cs.cmu.edu>, lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: > > This is well-known as one of Seymour Cray's concerns. In the Cray-1, > he was worried that standing waves could develop in the copper ground > plane of a circuit board. His answer was to make a machine with power > demand that was (I believe) completely independant of the data > flowing through it. This was a worry one machine before the Cray-1 - the Cyber 7600. (stuff deleted) > CMOS isn't like that. It's asymmetric, and cares about transitions: > 0=>1 takes more power than 1=>1. So, one can write worst-case > programs, which generate on-chip noise (mass transitions on the wide > datapath), or which generate board noise and heat (mass transitions > on the address and data pins). I'm not sure what cache activity > generally produces the most heat: it may depend on implementation. > (more deletions) > CMOS is wonderful, but the ECL/GaAs/BiCMOS folks talk an awful good > fight about how it's a different world on the other side of 50 MHz. Sure is. The ETA-10 had this problem in spades. This is why the ETA-10 air-cooled was limited to about a 12-13 ns clock (~80 MHz) before fratzing. There was a 15ns model (the model R) under development when CDC killed it. The liquid-nitrogen cooled behemoths could have gone just about as fast as one dared. The successor machine to the ETA-10G (the I model) was to be around 5 ns (200 MHz) in a breadbox-sized container of liquid nitrogen. Folks were talking about a 500 MHz board, but that was just hall talk. Note, the parts were ASIC CMOS. Still true today that the power required for the actual processing goes down, and the power required to cool the thing goes up. Neil Lincoln often joked that the ultimate machine would be thimble-sized and require one one-zillionth of a watt, but the cooling of the thimble would require one zillion watts. Rob Rob -- Rob Peglar Control Systems, Inc. 2675 Patton Rd., St. Paul MN 55113 ...uunet!csinc!rpeglar 612-631-7800 The posting above does not necessarily represent the policies of my employer.
jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) (11/18/89)
In article <150@csinc.UUCP> rpeglar@csinc.UUCP (Rob Peglar x615) writes: >In article <7000@pt.cs.cmu.edu>, lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes: > >> >> This is well-known as one of Seymour Cray's concerns. In the Cray-1, >> he was worried that standing waves could develop in the copper ground >> plane of a circuit board. His answer was to make a machine with power >> demand that was (I believe) completely independant of the data >> flowing through it. > >This was a worry one machine before the Cray-1 - the Cyber 7600. > Quoting from my Computer Architecture textbook: "Cray-1 modules are 6 inches wide. The distance across the board is about a nanosecond which is just about the edge time of the electrical signals. Unless due precautions are taken, when electric signals run around a board, standing waves can be induced in the ground plane. Part of the solution is to make all signals paths in the machine the same length. This is done by padding out paths with foil runs and IC packages. All told, between 10 and 20 percent of the IC packages in the machine are there simply to pad out a signal line. The other part of the solution is to use only simple gates and make sure that both sides of every gate are always terminated. This means that there is no dynamic component presented to the power supply. ... The final result is that there is just a purely resisitive load to the power supply." From: "The CRAY-1 Computer System," by Richard M. Russell. CACM, January, 1978. Maybe someone could comment on to what extent similar issues are important today as microprocessors approach the 50-100 MHz. range. -- Jeff Kuskin, Dartmouth College E-Mail: jskuskin@eleazar.dartmouth.edu
henry@utzoo.uucp (Henry Spencer) (11/19/89)
In article <17067@dartvax.Dartmouth.EDU> jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) writes: >[Cray 1] "...The other part of the solution is to >use only simple gates and make sure that both sides of >every gate are always terminated. This means that there >is no dynamic component presented to the power supply." In case anyone is curious, the significance of the "simple gates" part is that in the ECL technology used, simple gates have differential inputs and differential outputs. (Each logical bit is carried by two wires, one the inverse of the other.) So any time one wire is swinging from 0 to 1, its mate is swinging from 1 to 0, and any difference in power consumption is cancelled out. The larger chips use non-differential signals internally (to simplify chip layout) and externally (to conserve pins) and so this can't be done with them. -- A bit of tolerance is worth a | Henry Spencer at U of Toronto Zoology megabyte of flaming. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
henry@utzoo.uucp (Henry Spencer) (11/21/89)
In article <1989Nov19.030643.28335@utzoo.uucp> I wrote: >... in the ECL technology used, simple gates have differential inputs and >differential outputs... Oops, a small correction (must have been half asleep when I wrote that): the inputs generally aren't differential. However, if you terminate both sides of an output properly, it doesn't matter that one goes to some other gate's input and the other doesn't. -- A bit of tolerance is worth a | Henry Spencer at U of Toronto Zoology megabyte of flaming. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu