[comp.arch] GaAs CPUs

scarter@gryphon.COM (Scott Carter) (08/05/89)

In article <20981@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes:
>
>"The Prisma chip" is not a chip by a long shot.  Prisma is building a
>GaAs minisupercomputer, whose cpu will be hundreds (possibly thousands)
>of chips.  It happens to use the SPARC architecture (for software availability),
>but is in no sense a SPARC chip.  GaAs isn't there yet; maybe someone else
>can give an estimate of how long it will be before GaAs chips of several
>hundred thousands transistors are practical.  Prisma's systems, by the way,
>will be priced in hundreds of thousands of dollars.

"Several hundred thousand"??  Methinks you're starting to suffer from Intel
disease :).  An R3000 is only about 100K transistors, and contains rather
more than the IU.  Our MD484 GaAs microprocessor ("IU" would probably be
a better term for it) makes do fairly nicely with about 22K transistors,
which is achievable in today's GaAs processes.  A full system core is seven
chips:  CPU, FPU, branch target cache, two MMU/cache controllers, operand
memory pipeline controller, and system controller.  Total of about 200K
transistors, which compares reasonably to R3000(100K) + R3010(75K) + 
4xR3020 (??) + misc glue.

GaAs doesn't generally compete with the best ECL (e.g. BIT) for speed/density
product, but it does have the advantages of lower power, wide temperature
range, and immense radiation hardness (latter v. important for any space
application and some aviation applications).

Scott Carter
McDonnell Douglas Electronic Systems Company
(714)-896-3097