hmthaker@wateng.UUCP (02/25/87)
I am currently taking an "Advanced Computer Architecture"
course, and am doing a project on the Denelcor HEP (Heterogenous
Element Processor) machine.
However, I am having problems finding references.
I would appreciate suggestions as to where I can find any
material relating to the HEP, specifically, for the following:
1) Architectural Description
2) Pros and Cons of this architecture
3) Specific Applications
4) Reasons behind WHY they (Denelcor) chose this architecture.
The material that I DO have, includes the following :
a) Parallel MIMD Computations: HEP Supercomputer and Its
Applications
(note that is book is a collection of papers, and is
concerned more with parallel algorithms, as they
affect the HEP, than it is with describing the
machine itself)
b) Computer Architecture & Parallel Processing, by
Hwang & Briggs, pages 669 to 684.
(this gives a fair introduction to the HEP)
However, there are a few references that I am having trouble
locating :
i) Proceedings of the Workshop of Parallel Processing Using
the Heterogenous Element Processor, March 20-21, 1985.
ii) Heterogeneous Element Processor Principles of Operation,
Publication #9000001, Denelcor, Inc. 1981
Note that I did consider writing to Denelcor directly, but
I understand that they have gone out of business, so it would be
quite difficult to contact them.
Any suggestions as to where I could find the references, or
any other information would be appreciated. Please e-mail to the
following address :
watmath!wateng!hmthaker
(If there is an interest for this information, I will then post
the references to the net...)rajiv@im4u.UUCP (02/26/87)
Summary:Two more references. Sender:Rajiv N. Patel. > However, I am having problems finding references. >I would appreciate suggestions as to where I can find any >material relating to the HEP, specifically, for the following: > The material that I DO have, includes the following : > a) Parallel MIMD Computations: HEP Supercomputer and Its > Applications > (note that is book is a collection of papers, and is > concerned more with parallel algorithms, as they > affect the HEP, than it is with describing the > machine itself) > b) Computer Architecture & Parallel Processing, by > Hwang & Briggs, pages 669 to 684. > (this gives a fair introduction to the HEP) Some time back I too faced the same problem when I had to do a presentation on the HEP Architecture.I used the first two references mentioned above and two more which I have listed below. References: 1.Smith, B.J.,"A Pipelined Shared Resource MIMD Computer", Proc. ot the 1978 ICPP, pp 6-8. 2.Smith, B.J.,"Architecture and Applications of the HEP Multiprocessor Computer System", SPIE Vol.298 Real-Time Signal Processing IV (1981), pp 241-248. These two articles do not give the information of the HEP in detail but the second reference is the best infomation I could get on the HEP. More detailed information can be available from the National Labs. or The Univ. of Colorado at Denver.As far as I know these places had access to an HEP and must be knowing more about it. If any one would like to discuss the HEP, I know there isn't much to talk, you could send me mail. Rajiv N. Patel. ARPA: rajiv@im4u.utexas.edu UUCP:{inhp4,seismo}!ut-sally!im4u!rajiv
ron@brl-sem.UUCP (02/26/87)
In article <3178@wateng.UUCP>, hmthaker@wateng.UUCP (Hemi M. Thaker) writes: > I am currently taking an "Advanced Computer Architecture" > course, and am doing a project on the Denelcor HEP (Heterogenous > Element Processor) machine. I work for the U.S.Army Ballistic Research Laboratory. It is because of BRL the HEP was even built at all. We had one of the few ones ever delivered (there were about 7 in total). I helped with the UNIX port and some of the I/O system work done later. > 1) Architectural Description The HEP is a Multiple Instruction, Multiple Data Stream computer. The computer consists of one or more modules called PEMs. Each PEM could support 8-12 (depending on how define things) tasks. Tasks are what UNIX people think of as processes. Each task can have some larger number of "processes" which are parallel executions of the same code using the same data and instruction memory, but with different register sets. A hardware device called the SFU scheduled all these processes to try to keep all aspects of this machine as busy as possible. Even in the worst case, each PEM can execute eight UNIX process streams simoultaneously. Each intstruction stream running at about a MIP. Memory is divided into four parts: REGISTER MEMORY, a block of registers is available per PEM that the operating system can divide up among the processes as it sees fit. TABLE MEMORY (or CONSTANT MEMORY), more registers, but not writable to the user process. Since HEP is a load/store type machine, having certain constants always available in register is useful. PROGRAM MEMORY, this is ECL RAM that holds the program being executed. DATA MEMORY, data memory is ECL RAM. Unlike the other three types, data memory is available to all PEMs from through the "switch" (described below). Data Memory locations also have a semaphore bit called the "FULL/EMPTY" bit. The HEP memory referencing instructions can cause the process to be deselected until this bit is set appropriately. Unfortunately, all this is allocated with a single base register per type of memory. Makes UNIX-style stacks kind of fun. Multiple PEMs and the I/O systems are interconnected by the "switch." The switch is a packet switch which contains 64 bits of control information (address, full/empty bit, etc) and the 64 bit word. > 2) Pros and Cons of this architecture The architecture above, as well as few other things, make this thing really excell for UNIX. Unlike vector processors, we find that it's a little bit easier to get applications cranking along on the HEP. The switch caused some problems though, generally the way things were handled, it became loaded too easily. Most of the problems we had were with the original DENELCOR I/O system notions, not with the machine architecture itself. > 3) Specific Applications > 4) Reasons behind WHY they (Denelcor) chose this architecture. The machine was originally designed to solve partial-differential equation problems for hydrocode problems. Originally the machine was going to be an analog computer, then a hybrid, and finally they decided to just go for a slick all digital architecture. About the only thing we really got running on the thing before it was canned was Mike Muuss's ray tracing packages. Ray tracing consumes a lot of processor time and a bit of memory but is very applicable to parallel processing (each ray is just another process). > i) Proceedings of the Workshop of Parallel Processing Using > the Heterogenous Element Processor, March 20-21, 1985. Never seen this. > ii) Heterogeneous Element Processor Principles of Operation, > Publication #9000001, Denelcor, Inc. 1981 I have one, I guess if you sent me your name, I could xerox it for you. You probably don't need the whole thing. Most of it describes each instruction in detail. The neat parts about the memory synchronization and SFU are in the beginning. I could go more into other things like the I/O but you are probably not intersted in that. Let it suffice to say that it used a high speed buffer and lots of dedicated UNIBUSes. The UNIX was pretty slick to, I'd be willing to go into that if you want to hear.