markw@hpsal2.HP.COM (Mark Williams) (05/19/89)
This is a quick summary of the new IEEE Control/Status Register (CSR)
Standard. The standard (IEEE P21212) specifies generic architecture
intended to be used by different bus and/or vendor implementations to
facilitate interoperation.
Several industry-standard busses, including Futurebus+ (IEEE P896), SCI
(IEEE P1596) and Serialbus (IEEE P1394), are committed to implementing the
CSR Standard. In addition, VMEbus and Multibus II are adopting this CSR
standard for higher levels of their standards.
The CSR standard is scheduled for balloting in July '89. All interested
parties are invited to review and comment on the Standard. The draft CSR
Overview is available for review now from Dave James, CSR Chairman (at Apple
Computer, MS 22Y, 20525 Mariani Av., Cupertino, CA 95014 or EMAIL:
dvj@apple.com). Please request copies of the CSR Standard from Dave by
mail/EMAIL only -- do not post a request for a copy as a response to this
basenote.
I have summarized the CSR Overview below. (The rest of the CSR Standard
exists in rough draft form -- it will be reviewed in June). If you have
comments or questions about the CSR Standard, do post them to this basenote.
This is intended to be an open forum for discussion and review of the CSR
Standard.
CSR ARCHITECTURE:
The CSR standard specifies how processors bootup the system, implement
powerfail recovery, receive interrupts and control generic DMA services.
Boot Standard
During bootup, the standard defines how processors: search and identify
other nodes (modules), select a monarch processor, access non-volatile
memory to locate the boot device/s, execute self-test on nodes involved in
bootup, initialize memory, print status and accept commands via the standard
input and output devices, initialize bus converters in the boot path,
configure extended space for nodes and fetch boot code.
Powerfail Recovery
The CSR specification defines a model for power fail shutdown and recovery.
Requirements for notification of failure of primary and secondary power are
specified. The shutdown process is described. Recovery of processors'
local bus resources and remote bus resources is specified.
Unit Architecture
Architecture for units involved in the boot process is defined in detail.
Code source devices (disk, LAN), standard input/output devices (usually
keyboard/console), processors and memory are covered.
DMA Chaining, Interrupts
DMA requests are queued in request lists; status reports are queued in
similar completion lists.
Each node can send and receive interrupts to/from other nodes via a
register; they are cleared by writing to the register. Interrupts are
queued in lists, one for each of 32 interrupt levels.
Address Space
The CSR Standard defines standard address allocations for both 32 and 64 bit
physical address spaces. The 64 bit physical address version of the CSR
standard is a compatible superset of the 32 bit standard.
o In 32 bit physical space, memory is located in the range of 00000000-
DFFFFFFF.
o "Internal" or "special" space, which must not be used for bus visible
transactions, occupies E0000000-EFFFFFFF; it is intended be used for
internal oncard ROM.
o Between F0000000 and FFFFFFFF exist 1024 "busses", each of which has 64
"nodes". Each node has a 4K register address space.
Refer to CSR standard for more details.