amit@umn-cs.UUCP (Neta Amit) (10/26/87)
To support 0 wait-state on a 10 MHz CPU motherboard, one must use 100 nsec RAM chips. For 12 MHz, it's 80 nsec. For 15.5 MHz -- 65 nsec. Unfortunately, the 65 nsec chips are not exactly found in abundance. So what do they do? They make 286 boards running at 15.5 MHz with 1 wait state, and populate the board with 80 nsec chips, effectively slowing the CPU to 12.5 MHz. And what about 15.5 MHz 386 boards? Same problem, but THERE they use fast (50 nsec?) 64K static RAM chips, that serve as fast memory ``cache'' . In most cases, they claim (justifiably), this will make the 15.5 MHz machine run at close to 0 wait state. Now two questions: 1. Why don't they do the same trick with 286 boards (as far as I know)? Is there something more complex about the logic there or what? 2. Since most 15.5 MHz/1ws machines cannot select 12.5 MHz, are you better off (for whatever reason) with a 15.5/1, or with a 12.5/0 machine? -- Neta Amit U of Minnesota CSci Arpanet: amit@umn-cs.cs.umn.edu
farren@gethen.UUCP (Michael J. Farren) (10/27/87)
In article <2467@umn-cs.UUCP> amit@umn-cs.UUCP (Neta Amit) writes: >To support 0 wait-state on a 10 MHz CPU motherboard, one must use >100 nsec RAM chips. For 12 MHz, it's 80 nsec. For 15.5 MHz -- 65 nsec. This is only true if memory cycles are required to complete in one clock cycle. I don't have my 80286 data book here, so can't quote chapter and verse, but I'm almost dead certain that this isn't the case with that processor. >1. Why don't they do the same trick with 286 boards (as far as I know)? > Is there something more complex about the logic there or what? The '386 has the logic to handle cache built in, the '286 does not. >2. Since most 15.5 MHz/1ws machines cannot select 12.5 MHz, are you better > off (for whatever reason) with a 15.5/1, or with a 12.5/0 machine? The actual speed of the machine will be faster given a faster clock, even if you have wait-stated memory. All of the Intel processors are built with an instruction pipeline, which is filled as required with memory accesses. All instructions, therefore, execute internally at the full processor speed. Any time an instruction takes more time to execute than the time required to fetch itself from memory, you have a net gain. Determining what clock speed/wait state combination will provide the best net gain is fairly complex. Perhaps someone could post some numbers? -- ---------------- Michael J. Farren "... if the church put in half the time on covetousness unisoft!gethen!farren that it does on lust, this would be a better world ..." gethen!farren@lll-winken.arpa Garrison Keillor, "Lake Wobegon Days"
davidsen@steinmetz.steinmetz.UUCP (William E. Davidsen Jr) (10/27/87)
In article <2467@umn-cs.UUCP> amit@umn-cs.UUCP (Neta Amit) writes: [ discussion of cache for 286 and 386 machines ] | |1. Why don't they do the same trick with 286 boards (as far as I know)? | Is there something more complex about the logic there or what? PC Designs spec sheet shows 32k of cache on their GV286. The GV386 definitely has 64k of 35/45ns memory (35ns access, 45ns cycle), I have one. The performance boost ranges from 20-35%, depending on the program, mode, etc. It runs at 16MHz, not 15.5, which machines run 15.5? |2. Since most 15.5 MHz/1ws machines cannot select 12.5 MHz, are you better | off (for whatever reason) with a 15.5/1, or with a 12.5/0 machine? If the performance is equal otherwise, you get a boost in F.P. performance (assuming the 80287 runs at 2/3 CPU speed). Also, the 15.5 systems frequently run the expansion slots at half speed (7.75), while many 12.5 machines run the bus at full speed. The fast bus helps performance, but limits the number of boards which will work happily. To further muddy the waters, machines like the Tandy 4000 run interleaved memory. With 1MB the system runs 1w/s, with 2MB it runs 0w/s. Actually there may be a w/s on some accesses, but the net effect seems to be about the same as cache. -- bill davidsen (wedu@ge-crd.arpa) {uunet | philabs | seismo}!steinmetz!crdos1!davidsen "Stupidity, like virtue, is its own reward" -me