dheeraj@nile.cs.umd.edu (Dheeraj Sanghi) (09/15/89)
Hi, I wish to learn about RISC architectures, especially the MIPS, and SPARC. I would really appreciate, if someone could give me pointers to the books, journals, articles etc. explaining these (and other) RISC architectures, and also comparing them. I wish to apologize in advance, if this has been asked in recent past, but I don't read this newsgroup on a regular basis. Thanks, -dheeraj Dheeraj Sanghi (h):301-345-6024 (o):301-454-1516 Internet: dheeraj@cs.umd.edu UUCP: uunet!mimsy!tove!dheeraj Marriage is the sole cause of divorce.
mslater@cup.portal.com (Michael Z Slater) (09/16/89)
> I wish to learn about RISC architectures, especially >the MIPS, and SPARC. I would really appreciate, if someone could >give me pointers to the books, journals, articles etc. explaining >these (and other) RISC architectures, and also comparing them. I can't resist this opportunity to put in a plug for ourselves. There are a few books on RISC and lots of conference papers, and a few useful magazine articles, but I truly believe that nothing matches the range or depth of coverage of current, commercial RISC chips that has appeared in our Microprocessor Report newsletter. We've put together a reprint collection with all our RISC-related articles. We call it "Understanding RISC Microprocessors," and we sell it for $49. Subscriptions to the newsletter are $247 per year in US and Canada, $297 elsewhere (except Y54,000 in the Far East). The current issue has a detailed article on Intel's new i960CA, the first superscalar microprocessor. Michael Slater, Editor and Publisher, Microprocessor Report 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677 fax: 415/494-3718 email: mslater@cup.portal.com free sample issue sent on request; credit cards and purchase orders accepted