raj@hubcap.UUCP (R Parthasarathy) (11/18/87)
I've been investigating an issue regarding chip area distribution for processors. Computer Architects (those who are not particularly proficient in VLSI design and Layout) need a reasonable understanding of how much chip area is taken
up by the different resources on a chip in order to make design decisions.
Particularly, it is required to have a clear understanding of how much space
is saved by giving up a certain feature, so that something else may be included
instead. Normally, this kind of information is with persons having industrial
design experience and not with those dabbling in theoritical computer
architecture. Questions are ....
1. Are there any existing models which quantify the allocation of chip area for the various resources?
2. If so, then are these models very much technology dependent (i.e. Nmos,Cmos
.... etc.)?
3. Any references?
I would like to listen to the opinions of this newsgroup readers. Any takers?
Thanks in advance.
-------------------------------------------------------------------------------
Rajan Parthasarathy email:- {ihnp4,hao}!gatech!hubcap!raj
Box 5802, Univ Station raj@hubcap.clemson.edu
Clemson, SC 29632 Disclaimer:- I speak for myself.
Ph-(803)-654-3705
raj@hubcap.UUCP (Rajan Parthasarathy) (11/18/87)
I've been investigating an issue regarding the chip area distribution for
processors. Computer Architects (those not particularly proficient in VLSI
design and layout) need to have a reasonable understanding of how much chip
area is taken up by the different resources, in order to make design decisions.
Particularly, it is required to know how much chip area is saved by giving up
a certain feature in the architecture, so that something else may be included.
Normally, this kind of information is with persons having years of design
experience in the industry and not with those dabbling in thoretical computer
architecture (please, no flames if I have offended anyone). Questions are.....
1. Are there any existing models which quantify the allocation of chip area
between resources?
2. If so, then, are these models very much technology dependent (i.e. NMOS,
CMOS.. etc.)?
3. Any references?
I would like to listen to the opinions of this newsgroup readers. Any takers??
------------------------------------------------------------------------------
Rajan Parthasarthy email:-{ihnp4,hao}gatech!hubcap!raj
Box 5802, Univ Station raj@hubcap.clemson.edu
Clemson, SC 29632 General Disclaimer:I speak for myself.
Ph-(803)-654-3705raj@hubcap.UUCP (Rajan Parthasarathy) (11/18/87)
I've been investigating an issue regarding chip area distribution for current micro-processors. Computer Architects (those who are not particularly proficient in VLSI design and layout) need to have a clear understanding of how the area is allocated to different resources on a chip. Particularly, it is required to know how much of the area can be saved by giving up a certain feature in the design, so that something else may be included. Normally, this info is with persons having years of design experience in the industry and not with those dabbling in theoritical computer architecture (please, no flames if I have offended anybody). Questions are.... 1. Are there any existing models which quantify the allocation of chip area for the different resources on a chip ? 2. If so, are these models very much technology dependent (i.e.NMOS,CMOS etc.) ? 3. Any references ? I would like to listen to the opinions of this newsgroup readers. Any takers.. Thanks in advance -------------------------------------------------------------------------------- Rajan Parthasarathy email:- ....gatech!hubcap!raj Box 5802 Univ Station on internet:- raj@hubcap.clemson.edu Clemson, SC 29632 General Disclaimer:- I speak for myself. Ph-(803)-654-3705
howard@cpocd2.UUCP (11/19/87)
In article <679@hubcap.UUCP> raj@hubcap.UUCP (Rajan Parthasarathy) writes: >I've been investigating an issue regarding the chip area distribution for >processors. Computer Architects (those not particularly proficient in VLSI >design and layout) need to have a reasonable understanding of how much chip >area is taken up by the different resources, in order to make design decisions. Unquestionably. There are different ways to provide this feedback, however. >Particularly, it is required to know how much chip area is saved by giving up >a certain feature in the architecture, so that something else may be included. It's not just a question of the resources themselves, but also their interconnection, and the complexity of controlling them. Typical commercial microprocessors are 60% to 75% control, which is often difficult to explicitly represent in architectural studies. And it can often be cheaper to, say, put an extra adder in the chip, than to add routing and multiplexing to reuse an existing one that is idle but distant. >1. Are there any existing models which quantify the allocation of chip area > between resources? I'm not sure what you're asking for here. Do you mean quantify as in "measure the allocation for an existing design", or as in "suggest the appropriate allocation for a new design". These are very different problems unless you can synthesize complete designs rapidly! >2. If so, then, are these models very much technology dependent (i.e. NMOS, > CMOS.. etc.)? If not, they will not be very accurate. And suppose you are interested in the differences between different implementation strategies? One approach to this problem is to design in high-level, machine-readable specs that can be compiled (via "silicon compilation" or "logic synthesis" or whatever) directly into finished VLSI designs (or design fragments). Then precise numbers can be had. For example, I have sometimes used SCS's Genesil to do an architectural study (or a complete but poorly tested small design) in an afternoon, with detailed data available a few hours later. It is easy in this kind of environment to avoid gross architectural blunders; for example, I was once designing a chip for a 40 nS cycle time when I found that the large RAM I was planning to use implied a 72 nS minimum cycle time. This came to light during the first day of working on the chip, so I had lots of time to redesign with smaller, distributed RAMs. On the other hand, there are really no systems at present that make it easy to measure fine tweaks to the architecture, and architectural planning tools are poorly coupled to the backend design automation tools (which are sometimes just people!). -- Howard A. Landman {oliveb,hplabs}!intelca!mipos3!cpocd2!howard howard%cpocd2.intel.com@RELAY.CS.NET "You know it's gonna get stranger, so let's get on with the show."