rchampe@hubcap.clemson.edu (Richard Champeaux) (10/17/89)
I remember a while ago when they were developing 1 Meg DRAMS, they said that they had to be run off of 3.3v supplies to reduce power dissapation. Looking in a TI databook, I notice that TI's 1 Meg DRAMS (TMS4C1024) use a 5v supply and have TTL compatable inputs/outputs. My guess is that they run the I/O buffers off of the 5v supply and have a 3.3v regulator inside for the rest of the chip. My question is, are all 1 Meg DRAMS like this? Thanks for any help. Rich Champeaux (rchampe@hubcap.clemson.edu)
henry@utzoo.uucp (Henry Spencer) (10/17/89)
In article <6797@hubcap.clemson.edu> rchampe@hubcap.clemson.edu (Richard Champeaux) writes: >I remember a while ago when they were developing 1 Meg DRAMS, they said >that they had to be run off of 3.3v supplies to reduce power dissapation... This is one of these "gonna have to make big changes real soon now" claims that keeps running around, and keeps getting shot down when people discover that it's cost-effective to work *really hard* to avoid the pain of making such changes. Other such claims are "gonna have to drop silicon and go to gallium arsenide real soon now", "gonna have to go to highly-parallel machines to get any further speed increase real soon now", and "gonna have to drop optical lithography and go to electron beams or X-rays real soon now". (One of the gems of my collection is an unintentionally-hilarious paper from an IEEE conference proceedings that proves, in some detail, that it is impossible to build 64Kb DRAMs with optical lithography.) "Gonna have to go to 3.3V for the next generation of memories" has been around for fifteen years or so. -- A bit of tolerance is worth a | Henry Spencer at U of Toronto Zoology megabyte of flaming. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
eric@snark.uu.net (Eric S. Raymond) (10/19/89)
In <1989Oct17.154651.16073@utzoo.uucp> Henry Spencer wrote: > Other such claims are "gonna have to drop silicon and go to > gallium arsenide real soon now", "gonna have to go to highly-parallel > machines to get any further speed increase real soon now", Don't forget "gonna have to go to exotic %s technology that no one can afford to manufacture onto commodity boards real soon now", where %s can read "interconnect", "heat dissipation", or "reduced-RF-emission". There are situations in prognosticating technology when blissful ignorance and an eye on the trend curves yields better predictions than `expert' opinion with all its preconceptions. If I really knew electronic engineering I'm sure I'd think these were insuperable problems for the next generation. As it is...well, we've heard all these doleful dirges before. -- Eric S. Raymond = eric@snark.uu.net (mad mastermind of TMN-Netnews)
eric@snark.uu.net (Eric S. Raymond) (10/19/89)
In <1989Oct17.154651.16073@utzoo.uucp> Henry Spencer wrote: > (One of the gems of my collection is an unintentionally-hilarious paper > from an IEEE conference proceedings that proves, in some detail, that it > is impossible to build 64Kb DRAMs with optical lithography.) O.K., now please tell us which limiting assumption went wrong and why. -- Eric S. Raymond = eric@snark.uu.net (mad mastermind of TMN-Netnews)
henry@utzoo.uucp (Henry Spencer) (10/19/89)
In article <1T9NpG#464lr4=eric@snark.uu.net> eric@snark.uu.net (Eric S. Raymond) writes: >> (One of the gems of my collection is an unintentionally-hilarious paper >> from an IEEE conference proceedings that proves, in some detail, that it >> is impossible to build 64Kb DRAMs with optical lithography.) > >O.K., now please tell us which limiting assumption went wrong and why. Hey, I'm a systems programmer, not a chip designer -- *I* don't know! :-) If enough people are interested, I can dig out the paper and post the gist of the argument, so the real chippies :-) can pick holes in it. -- A bit of tolerance is worth a | Henry Spencer at U of Toronto Zoology megabyte of flaming. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu