sbw@naucse.UUCP (Steve Wampler) (08/23/87)
I have a question on addressing registers on register file
machines (I think that is the term - machines with overlapping
register windows such as RISC I and II). How do real machines
implement this?
I have minor dealings with a company that is building a similar
machine, except that they have been unable to get register addressing
to work. Some additional information might guide people's answers:
It seems to me that, for register addressing to be effective, there
should be no difference in the use of the address versus a
'conventional' memory address. I.e. anywhere, anyway a memory address
is used, a register address would also work. For example, one
should be able to allocate a (small) array in registers, take the
address of the first position, then step through the array a byte
at a time. Do real machines allow this? Must one step through
a register width at a time? Further, if the register file overflows
and some windows are moved out, or if it later underflows and
some (possibly different) windows are moved in, there so be no
difference (other than possibly performance) from the point of
view of the user of the register address.
This particular machine has the least significant byte on the right
in registers and on the left in memory, could that be the reason
they were having troubles, or is my view of how register files
operate that unreasonable from a hardware point of view?
I think that the IBM RT RISC machine doesn't operate with a
register file, and doesn't have a 'CAR' compute address of a
register machine. I would love to have *accurate* information
on other machines.
Please email me, I don't get out this way very often. Thanks.
Steve Wampler
{....!arizona!naucse!sbw}