[comp.arch] TLB consistency on shared-memory MIMD multiprocessors

teller@cmcl2.NYU.EDU (Patricia J. Teller) (06/23/87)

Does anyone know how TLB consistency is guaranteed on commerical 
Pat Teller (teller@pat.ultra.nyu.edu or teller@cmcl2.arpa)
multiprocessors such as those manufactured by Sequent, Alliant, or Convex?

collins@encore.UUCP (Jeff Collins) (06/29/87)

In article <16984@cmcl2.NYU.EDU>, teller@cmcl2.NYU.EDU (Patricia J. Teller) writes:
> Does anyone know how TLB consistency is guaranteed on commerical 
> multiprocessors such as those manufactured by Sequent, Alliant, or Convex?