shrenik@pyramis.Eng.Sun.COM (Shrenik Mehta) (08/03/90)
NEW BOOK ANNOUNCEMENT: ---------------------------------------------------------------------------- HARDWARE MODELING WITH VERILOG HDL ---------------------------------- by Eliezer Sternheim Interpretive Systems Rajvir Singh Nexgen Microsystems Yatin Trivedi Sun Microsystems ---------------------------------------------------------------------------- This is the first book about the Verilog Hardware Description Language which has become a standard for designing digital systems and VLSI devices. The book is primarily written for those who have prior knowledge of the Verilog HDL and want to learn more about designing complex devices and large systems. This book is also useful to designers with no Verilog experience but with exposure to other hardware description languages or high level programming languages. A separate chapter is devoted to the introduction of Verilog HDL with emphasis on the behavioral aspects of the language. The book also contains a separate chapter describing some useful tips and techniques in modeling debugging. Two appendices give formal syntax of the language and its reserved keywords. The book contains the following chapters: 1. Why Hardware Description Languages? 2. Anatomy of the Verilog HDL 3. Modeling a Pipelined Processor 4. Modeling System Blocks 5. Modeling Cache Memories 6. Modeling Asynchronous I/O: UART 7. Modeling a Floppy Disk Subsystem 8. Useful Modeling and Debugging Techniques Appendix A: Verilog Formal Syntax Definition Appendix B: Verilog Keywords Each chapter on modeling first describes a piece of hardware, then develops and explains its Verilog model, and at the end, provides a complete listing of the Verilog model. The stress has been to design a piece of hardware at a higher level of abstraction which can be implemented at gate level by some appropriate synthesizer. Check with local bookstores or to order a copy of the book write to the publishers: Automata Publishing Company PO Box 50335 Palo Alto, CA 94303, USA Fax: 415-855-9545 Phone: 408-255-0705 -------------------------------------------------- VOLUME DISCOUNT AVAILABLE FROM PUBLISHER -------------------------------------------------- The souce code for the models can be purchased from the publisher. ************************************************************************** DISCLAIMER: This posting is done as a favor to the authors and I have no personal monetary benefits ************************************************************************** Shrenik Mehta Sun Microsystems shrenik@Eng.Sun.COM
jcallen@Encore.COM (Jerry Callen) (08/03/90)
In article <140081@sun.Eng.Sun.COM> shrenik@pyramis.Eng.Sun.COM (Shrenik Mehta) writes: > [Announcment of new book on Verilog Hardware Description Language] > >This is the first book about the Verilog Hardware Description Language >which has become a standard for designing digital systems and VLSI devices. >The book is primarily written for those who have prior knowledge of the >Verilog HDL and want to learn more about designing complex devices and large >systems. Lemme see now, that's "Verilog Hardware Description Language" - by golly, that's VHDL! I've been hearing all about that lately; something about VHDL use mandated on government work or something. Geez, sounds great! Seems like there is potential for confusing Verilog HDL with: VHSIC Hardware Description Language (VHDL) where VHSIC stands for Very High Speed Integrated Circuit. _This_ VHDL was designed by Intermetrics and is the one the government likes. Of course, for all I know, Verilog HDL may in fact _be_ VHSIC HDL. The language is (I believe) in the public domain, and Intermetrics licenses its VHDL compiler to other companies; I think other companies have also written VHDL compilers. Does anyone KNOW if Verilog HDL is VHSIC HDL? This is not meant as a flame at Verilog (or anyone); I just wanted to head off some possible confusion. -- Jerry Callen jcallen@encore.com Claimer: I used to work at Intermetrics. Several Intermetricians have written a book on VHSIC HDL; I don't recall the title offhand.