[comp.arch] RISC and fast I/O

jbuck@janus.Berkeley.EDU (Joe Buck) (05/10/91)

[ someone writes: ]
>>Also, is there anything to prohibit a RISC based machine from having a high
>>speed IO subsystem?  Would adding this make the machine cost as much as a
>>3090?

In article <1991May9.144406.20558@vlsi.waterloo.edu> ward@vlsi.waterloo.edu (Paul Ward) writes:
>I don't know, but it is an interesting question.  Do you have $20,000,000 ?
>We can try a little experiment.  :-)

Dave Patterson and his group are primarily researching I/O these days
(Patterson coined the term "RISC" and the RISC-1 and RISC-2 projects at
U.C. Berkeley eventually turned into the Sparc).

I expect that more and more research work will turn to the problems of
how to design cheap memory systems that deliver supercomputer performance,
and how to increase I/O bandwidth, and there's no reason that this should
cost $20M (though initially it won't be cheap).

--
Joe Buck
jbuck@janus.berkeley.edu	 {uunet,ucbvax}!janus.berkeley.edu!jbuck