mash@mips.COM (John Mashey) (08/07/89)
In article <38139@stellar.UUCP> wright@sol.UUCP () writes: .... >Honeywells were basically IBM ripoffs with a special Gray-to-binary >instruction added so they could work on radars on the DEW line. >They had some interesting features; not only did they have an >execute (XEC) instruction that would execute the instruction at the >effective address, they had execute double (XED) that would execute >the two instructions starting at the effective address. Since the .... > >The other feature I've not seen elsewhere was the repeat instruction. >This had the effect of repeatedly executing the instruction following >the repeat (RPT), or the two instructions following (RPD) up to 256 >times. You could specify condition code settings that would end >the iteration before the count ran out. There was even repeat-link, .... This is really great stuff for placing the usual RISC-vs-CISC wars in better context: compared to some of the older mainframe architectures, 80386s, 68Ks, even S/360s and VAXen are about as RISCy as they come. In fact, this leads to an interesting question for the old-timers: how about more reminiscing of instruction-set-architecture features of the machines designed in the 50s and 60s, that have essentially disapeared in those designed in the 70s and 80s...? -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
gregg@cbnewsc.ATT.COM (gregg.g.wonderly) (08/07/89)
> In article <38139@stellar.UUCP> wright@sol.UUCP () writes: >Honeywells were basically IBM ripoffs with a special Gray-to-binary >instruction added so they could work on radars on the DEW line. >They had some interesting features; not only did they have an >execute (XEC) instruction that would execute the instruction at the >effective address, they had execute double (XED) that would execute >the two instructions starting at the effective address. >... I have seen some discussion of the TMS-9900 microprocessor, but I don't recall if it was here. The 9900 has a similar instruction, X, whose parameter is an effective address of the instruction to execute. The really wild thing is that, X R4, is valid because registers are in memory. BLWP is effectively a free context switch. The 9900 has only three hardware registers. The status register, the PC, and the workspace pointer, which is the address of the registers in memory. When you want to doodle with a piece of memory that is relatively small, you can load the WP with the starting address and do you diddling. Basically it goes something like MOV @DIDDLE_AREA,R1 MOV @NEWCODE,R2 BLWP R1 R1 is effective address of descr JMP AROUND NEWCODE EQU $ do some stuff using R0 though R12 for whatever purposes, maybe fast hardware memory mapped I/O. RTWP Return to where we came from with old regs restored AROUND EQU $ continue doing something else The other, maybe not so obvious, thing is that you can load object code into registers and just call it or branch to it. Given a larger address space than just 64K and a MMP, this architecture could provide some unique opportunities for code size reduction. Also, in C, passing the address of a register variable would have meaning. -- ----- gregg.g.wonderly@att.com (AT&T bell laboratories)
mrc@Tomobiki-Cho.CAC.Washington.EDU (Mark Crispin) (08/08/89)
In article <24889@winchester.mips.COM> mash@mips.COM (John Mashey) writes: >In fact, this leads to an interesting question for the old-timers: >how about more reminiscing of instruction-set-architecture features of the >machines designed in the 50s and 60s, that have essentially >disapeared in those designed in the 70s and 80s...? I don't know if any of this has been mentioned yet: The PDP-8 only had 8 machine instructions, but oh that 8th instruction! Opcode 7 was OPR, which interpreted the following 9 bits as various miscellaneous non-memory referencing operations. A couple of the bits identified a particular "group" of instructions (= the interpretation of the other bits). You could "microprogram" instructions of the same group together so they all got executed at the same time, with amazing and useful results. The PDP-10 didn't have condition codes, but it did have a test instruction, which had 64 opcodes, depending upon what you tested (right half from immediate, left half from immediate, register from memory, register from memory swapped), what you did with the test bits (no modification, set to zeros, set to ones, complement), and under what conditions you would skip the next instruction (never, always, if all masked bits zero, if any masked bit one). This (along with the other skip instructions) let you create elaborate if chains that were far more elaborate than was possible with the if/else of high level languages. One cute trick was: TRCE AC,B1+B2 TRCE AC,B1+B2 TRCE AC,B1+B2 where B1 and B2 are two separate single right half bits. TRCE is Test Right half from immediate, Complement the masked bits when done, and skip if any masked bits were Equal to zero. This would swap the state of the two bits. The third instruction could have been TRC (never skip) but it can never skip (figure it out for yourself) and it's easier to remember as three TRCE's. I used to call this the "tricky-tricky trick" based on the hacker pronounciation of those opcodes. The PDP-10 had every form of bitwise logic instruction, including those instructions that were normally not useful. One such instruction was the equivalence instruction, which compared two values and returned 1 for each bit in the two values which was equal. In other words, equivalence was the opposite of exclusive-OR. One very common type of register index value was the AOBJN-pointer, which had a negative count in the left half and an index in the right half. The AOBJN (Add One to Both Halves and Jump if Negative) instruction would go at the tail of a loop and would cause an interation until the count ran out. Now, if you had a *positive* count in a register (say T1) and needed to set up an AOBJN pointer in T1 with a non-zero initial index (say FOO), you would need something like: MOVN T1,T1 ; negate T1 (or MOVNS T1) HRL T1,T1 ; copy right half to left (or HRLS T1) HRRI T1,FOO but with equivalence, you could do: HRLOI T1,-1(T1) ; put C(T1)-1 into left half, -1 in right half EQVI T1,FOO ; equivalence with 0,,FOO The first instruction combines a subtract of 1, load into left half, and set to ones of the right half. Since the left half of an immediate is 0, the equivalence does a one's-complement of the left half (which is a two's- complement of the original value due to the subtract of 1) and a copy of the right half. Mark Crispin / 6158 Lariat Loop NE / Bainbridge Island, WA 98110-2020 mrc@CAC.Washington.EDU / MRC@WSMR-SIMTEL20.Army.Mil / (206) 842-2385 Atheist & Proud / 450cc Rebel pilot -- a step up from 250cc's!!! tabesaserarenakerebanaranakattarashii...kisha no kisha ga kisha de kisha-shita sumomo mo momo, momo mo momo, momo ni mo iroiro aru uraniwa ni wa niwa, niwa ni wa niwa niwatori ga iru