aglew@crhc.uiuc.edu (Andy Glew) (12/06/90)
[Peter A. Buhr writes:] >I would like to announce, to any interested parties, the availability of >Version 4.3 of the uSystem (pronounced micro-system), a light-weight >tasking facility and a companion monitor preprocessor for use in C on UNIX >systems. > > ... > >4. There was a bug in the multiprocessor MIPS version of the uSystem that >caused applications to hang. The assembler was interchanging store >instructions to fill the pipeline. This caused locks to be released >prematurely. This is a fundamental problem for any application that tries >to do its own synchronization, for example, Dekker's or G.L. Peterson's >algorithms may not work because the assembler could reorder stores >regardless of what you specify in the C code. After having worked on the >MIPS machine for several months, it is clear to us that it was not designed >with concurrency in mind. It is a very difficult machine to work on from a >concurrency standpoint. We are discovering the same to be true of the >Sparc. So much for RISC architectures. :-) Let me defend RISC architectures by pointing out that modern computer architectures that are designed for concurrency usually do not support write-ordering. Writes can be reordered by the compiler or by buffers in the memory system, so mutual exclusion algorithms that rely on write-ordering will not work. Modern architectures support concurrency with weak consistency [Dubois] or release consistency [Hennessy, DASH] or sender- and receiver- consistency models [Glew]. Essentially, this means that memory consistency is guaranteed only after the execution of special RMW synchronization instructions (with various features to enhance performance). These models crystallize and extend industrial practice - many real, high performance, parallel processors did not support write ordering as long as 10 years ago. The MIPS R[23]000 architecture does not have any atomic RMW operations, but most other RISCs do: exchange-with-memory on the MC88100, swap and load-store-unsigned-byte on SPARC. I'm told that the MIPS R6000 has (had?) synchronization instructions, but I have not seen the technical details of these. -- Andy Glew, a-glew@uiuc.edu [get ph nameserver from uxc.cso.uiuc.edu:net/qi]