keith@mips.COM (Keith Garrett) (05/03/89)
In article <396@dalcsug.UUCP> erskine@dalcsug.UUCP (Neil Erskine) writes: >In article <6658@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes: >>[bandwidth limited by capacitive loading due to static protection and fan-out] > > I'm no engineer, but if the capacitive pad loads are >restricting the speed of off-chip signalling, why not dispense with >them, and provide the static protection at the board level? This >might make board assembly more costly (due to the increased care >required), and the board itself more costly (it might have to be >encased in metal), but if it gives a significant degree of additional >speed, the bother and expense seem worth it. Alternatively, there may >be some reasons why board level protection can't do the job; in which >case what are those reasons? ESD (static) protection is required to protect the ic's during handling before they are place on boards. the need increases with the smaller devices used in advanced technologies. -- Keith Garrett "This is *MY* opinion, OBVIOUSLY" UUCP: keith@mips.com or {ames,decwrl,prls}!mips!keith USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086
davidb@inmos.co.uk (David Boreham) (05/09/89)
Several posters have refered to removing ESD protection on chip pads, and alluded to consequent speed advantages. Mabe I'm missing something but as far as I know the reason why off-chip signals are slower than on-chip ones is a combination of the following: 1) Much larger capacitance (25pf minimum or 50--100 pf for busses). 2) The need to drive current. 3) The need to drive over a wide voltage range (0--5v) in order to be compatible with TTL devices. 4) Off-chip signals need to be tested on a tester. Testers are not generally capable of resolving very accurate timing (on microprocessors) and require large (50pf or so) capacitances to be driven during testing. I think these are probably ranked in order of importance. ESD must surely be less important than these. -- David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos-c!davidb +44 454 616616 ex 543 | Internet : @col.hp.com:davidb@inmos-c
jesup@cbmvax.UUCP (Randell Jesup) (05/23/89)
In article <1450@brwa.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes: >Several posters have refered to removing ESD protection on chip >pads, and alluded to consequent speed advantages. Mabe I'm missing >something but as far as I know the reason why off-chip signals are >slower than on-chip ones is a combination of the following: > >1) Much larger capacitance (25pf minimum or 50--100 pf for busses). ... >I think these are probably ranked in order of importance. ESD must surely >be less important than these. Actually, I believe ESD is the prime reason for (1) above, so it is the biggest target (for very high speed designs). Of course, I'm just a software guy, what do I know? ;-) -- Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup
ron@motmpl.UUCP (Ron Widell) (05/24/89)
In article <6951@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes: >In article <1450@brwa.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes: >>Several posters have refered to removing ESD protection on chip >>pads, and alluded to consequent speed advantages. Mabe I'm missing >>something but as far as I know the reason why off-chip signals are >>slower than on-chip ones is a combination of the following: >> >>1) Much larger capacitance (25pf minimum or 50--100 pf for busses). > > Actually, I believe ESD is the prime reason for (1) above, so it >is the biggest target (for very high speed designs). > > Of course, I'm just a software guy, what do I know? ;-) > >-- >Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup Both of you are right (and wrong :-)). The ESD protection diodes are a significant source of the capacitive load which the inputs present to a transmission line; but, since we do have to think of transmission lines (and it seems like few designers/engineers using MOS or TTL circuits *do* think that way) we must also consider the capacitive load which the outputs must drive. On a poorly-designed circuit board (or whatever) this can represent significantly more capacitance than the fan-out count of all of the inputs would indicate. This necessitates some rather large buffers on the outputs, which means greater power dissipation; and MOS, in particular, tends to slow down as it heats up. There's still no free lunch. Interestingly, to me at least, we find that the biggest problem with the *really* high speed circuits (500MHz to 1.2GHz ECL) is that the lead inductance of the high-pin-count packages is the real killer. At first blush, TAB seems the way to go. Regards, -- Ron Widell, Field Applications Eng. |UUCP: {...}mcdchg!motmpl!ron Motorola Semiconductor Products, Inc., |Voice:(612)941-6800 9600 W. 76th St., Suite G | I'm from Silicon Tundra, Eden Prairie, Mn. 55344 -3718 | what could I know?
davidb@inmos.co.uk (David Boreham) (05/31/89)
In reply to Randell Jesup's comment on my posting about whether ESD protection is a significant reason for chip--chip signals being slower than on-chip :- The capacitance which I was refering to is the PCB trace capacitance and the input capacitance of the chips to be driven. This is typically 20--50pf. I fail to see where you can get anywhere near that capacitance from any kind of pad protection circuit. I'd be interested to know where the original idea about ESD protection slowing down device signals came from --- it sounds most bizarre. -- David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos-c!davidb +44 454 616616 ex 543 | Internet : @col.hp.com:davidb@inmos-c