lindsay@k.gp.cs.cmu.edu (Donald Lindsay) (05/05/88)
Actually, there is a trivial way to keep virtual caches coherent. Just widen the address bus, so that the virtual address is transmitted along with the physical address. This may sound pretty silly, since it costs perhaps 32 extra signals. (A page number is about 20, plus you need to identify the address space.) However, three comments: - the extra signals don't actually go to memory: they are an "inter-processor coherency bus". If all the processors are on the same circuit board, this could actually be a good way to go. - if the OS keeps one physical address at multiple virtual addresses, then this scheme is still no worse than other schemes. - if IO devices generate physical addresses (only), then reverse-mapping schemes have the advantage. Which brings up the question, why don't we do IO with virtual addresses? We have living proof that it can be done. Why isn't it catching on? -- Don lindsay@k.gp.cs.cmu.edu CMU Computer Science
aglew@urbsdc.Urbana.Gould.COM (05/10/88)
>Which brings up the question, why don't we do IO with virtual addresses? >We have living proof that it can be done. Why isn't it catching on? > > Don lindsay@k.gp.cs.cmu.edu CMU Computer Science Gould's NP1 UIOM (Universal I/O Module) can do I/O using I/O Command Blocks containing virtual addresses. I don't know if the OS is using it at the moment (not my department, sorry), but the prospect of using it to do I/O to dedicated devices without much OS intervention is attractive.
bartlett@encore.UUCP (John Bartlett) (05/11/88)
>Which brings up the question, why don't we do IO with virtual addresses? >We have living proof that it can be done. Why isn't it catching on? > > Don lindsay@k.gp.cs.cmu.edu CMU Computer Science I have considered this from time to time. For specifically allocated channels, like disk DMA channels, it may make sense. For a device that can potentially support concurrent traffic for more than one process, you need an MMU for each thread of control, and suddenly you have an allocation problem. The other thing that consistently gets in the way is that IO has this tendency to require deterministic delays so various buffers don't overrun and the like. MMUs dont lend themselves well to that. IO also doesn't know what to do with a fault. All in all, considering that I/O set up time does not seem to dominate our processors, we have chosen to continue to let the O.S. remap stuff into the appropriate physical addresses. John Bartlett {ihnp4,decvax,allegra,linus}!encore!bartlett Encore Computer Corp. 257 Ceder Hill Street Marlboro, Mass. 01752 (617) 460-0500 Opinions are not necessarily those of Encore Computer Corp.