pardo@june.cs.washington.edu (David Keppel) (08/10/88)
>>mcdonald@uxe.cso.uiuc.edu writes: >>>[ Core has destructive read ] >henry@utzoo.uucp (Henry Spencer) writes: >>[ So do DRAMs ] ward@cfa.harvard.EDU (Steve Ward) writes: >[ No they don't, they're just shift registers ] This flies in the face of what I was told in digital design. If anybody knows differently, please tell me (e-mail) and I'll summarize. Here's what I remember of what I was told: A dynamic RAM is created by making lots of "wells" in the substrate (say, p-type silicon) and filling the wells with another (n-type) silicon. The substrate is, say, grounded, so there is a (small) capacitive effect between the well and the fill. Each capacitor is tied to the gate of a transistor, so that when you put current in the collector, current will come out the emitter if and only if the capacitor was charged. In the actual construction of the DRAM, the capacitor is actually part of the transistor. The DRAM is organized as an array of transistors, say 256 x 256. Each collector is tied to one of 256 "row" wires, so each "row" wire is is connected to 256 transistors. Each collector is tied to one of 256 "column" wires. Each column wire is tied to 256 transistors, and NONE of the transistors on a column wire share a row wire. The row wires are connected to a demultiplexer taking 8 bits in and turning on exactly one of the 256 row wires. Each column wire is connected to an amplifier. The amplifier is unusual, in that at the begining of a read cycle it is initially set to be unstable, niether on nor off, but half-way in-between (e.g., 2.5 volts on a 0/+5v supply). When one of the row wires is turned on, 256 transistors, one on each column-wire, can potentially conduct; those that have their gates connected to charged transistors *do* conduct, and drive the unstable amplifier high. Those that have their gates discharged don't conduct, and a pull-down resistor on the column wire pulls the amplifier low. The only trick in this is that the capacitor, if it was charged initially, has since been discharged as it provided current for the transistor to conduct. The on/off-ness of the particular row has moved out of the capacitors and in to the amplifiers. The amplifiers (which are driving multiplexers and other amplifiers that drive the data lines) *also* drive the column wires. Since the capacitor is actually part of the transistor, the voltage appearing on the column wire will recharge the capacitor. At least that's what mom told me. ;-D on ( Manhattanizing the computer architecture skyline ) Pardo -- pardo@cs.washington.edu {rutgers,cornell,ucsd,ubc-cs,tektronix}!uw-beaver!june!pardo
ward@cfa.harvard.EDU (Steve Ward) (08/11/88)
In article <5460@june.cs.washington.edu>, pardo@june.cs.washington.edu (David Keppel) writes: > >>mcdonald@uxe.cso.uiuc.edu writes: > >>>[ Core has destructive read ] > >henry@utzoo.uucp (Henry Spencer) writes: > >>[ So do DRAMs ] > ward@cfa.harvard.EDU (Steve Ward) writes: > >[ No they don't, they're just shift registers ] > > Each capacitor is tied to the gate of a transistor, so that when you > put current in the collector, current will come out the emitter if and > only if the capacitor was charged. In the actual construction of the > DRAM, the capacitor is actually part of the transistor. > > The only trick in this is that the capacitor, if it was charged > initially, has since been discharged as it provided current for the > transistor to conduct. The on/off-ness of the particular row has > moved out of the capacitors and in to the amplifiers. The amplifiers > (which are driving multiplexers and other amplifiers that drive the > data lines) *also* drive the column wires. Since the capacitor is > actually part of the transistor, the voltage appearing on the column > wire will recharge the capacitor. > > {rutgers,cornell,ucsd,ubc-cs,tektronix}!uw-beaver!june!pardo Well folks, it looks like the DRAM memory cell content is essentially destroyed by readout, though by design it looks like rewrite/refresh is inherent in reading. I guess the amplifiers have a sample/hold or similar capability as the data can be held on the bus for a variable period of time, which I speculate is well beyond the gate capacitor discharge time. The similarities are quite evident between the old magnetic core sense/restore circuit and the above DRAM description. Now that I know all about DRAM's, will somebody give me some? :-) (only 256K and 1M denominations accepted!) Steve Ward ward@cfa
mangler@cit-vax.Caltech.Edu (Don Speck) (08/11/88)
In article <5460@june.cs.washington.edu>, pardo@june.cs.washington.edu (David Keppel) writes: > Each capacitor is tied to the gate of a transistor, so that when you > put current in the collector, current will come out the emitter if and > only if the capacitor was charged. In the actual construction of the > DRAM, the capacitor is actually part of the transistor. Although I think that Fairchild actually made a 4K dRAM in I^2 L (Integrated Injection Logic) in the late 1970's, bipolar transistors make leaky switches. MOSFETS are the rule, and the capacitor is a MOS capacitor. MOSFETS isolate so well that the dominant leakage is through parasitic reverse-biased diodes, not the transistors. The first dRAM, the Intel 1103 (1K bits) circa 1971, used one MOSFET to place charge onto the gate of an output transistor, and a third transistor for read select. Writing was 32 bits at a time; to write one bit was a read-modify-write affair, like magnetic core. The 3-transistor dRAM cell was abandoned when the 1-transistor cell was invented at IBM in the early 1970's, although the Mead & Conway VLSI text in 1978 re-popularized it among academics. It "looks digital" but is actually plagued with analog problems. The 1-transistor cell, used in the 4K through 4M chips, stores charge under the gate of a MOS capacitor (typically with a very thin dielectric) and dumps it onto a bit line. The final state of the bit line will vary by a few tenths of a volt depending on what was stored. Meanwhile, a reference cell sets an identical bit line to an intermediate value. A 2-transistor positive-feedback differential amplifier (its outputs cross-coupled to its inputs) pulls down on whichever input has lower voltage. The amplifier must be powered down while its inputs are being set up, and turned on slowly. Then the higher-voltage input is pulled up, typically with a similar amplifier built with the complementary device. Some of the mid-1970's 4K dRAMs used two capacitors per bit for differential storage, instead of a reference cell. The noise immunity is better, and analysis is markedly easier. The 2-transistor cell can be thought of as a 4-transistor cell with the differential pair shared among many cells. Static RAMs go through the same kind of read regeneration on a cell-by-cell basis that a dRAM does on a column-by-column basis. Writing either a dRAM or sRAM is done by simply overpowering one of the sense amplifiers, forcing the bit lines to the desired value, while the remaining amplifiers perform a normal read/refresh. There is no need for read-modify-write except in the case of chips with builtin ECC. A static-column dRAM leaves the amplifiers fully powered up until RAS is deasserted, so that they can drive the output wires more than once. In article <11815@steinmetz.ge.com> oconnor@nuke.steinmetz (Dennis M. O'Connor) writes: > ( I think on some designs the data is actually > INVERTED when re-written, and one bit per word is kept around to > keep track of wether the bits are in true or complement form. ) This is only advantageous with 3-transistor cells, whose read data is the inverse of what was written. However, half of the cells in a 1-transistor dRAM array read and write inverted data because they connect to the inverting side of the differential sense amplifier. Don Speck speck@vlsi.caltech.edu {amdahl,ames!elroy}!cit-vax!speck