mark@mips.COM (Mark G. Johnson) (04/16/88)
In article <27292@yale-celray.yale.UUCP>, tam-hong@CS.Yale.EDU (Hong Tam) says > Does anyone know any references about the RISC architecture > with floating point co-processor? I tried very hard but still > couldn't find any papers written about it. One such architecture is the MIPS R2000, which dedicates "coprocessor 1" to (IEEE compatible) floating point ..... it's implemented as a chip called the R2010. You can read about it in: Ries, Paul S., "An 8 MFLOP Floating-Point Coprocessor for a RISC Microprocessor", conference proceedings of IEEE Electro, 10 May 1988. Also, as dan@apple.UUCP (Dan Allen) pointed out in this newsgroup <8306@apple.Apple.Com>, > .... [wait] until the next issue [of IEEE Micro] which is on > RISC stuff. One of the papers in that issue (June 88) covers the FP coprocessor for MIPS' newer CPU chip. Other RISC FP coprocessor ideas: 1. The IBM PC/RT uses a RISC processor and, I believe, a Motorola MC68881 for floating point coprocessor. 2. The Sun-4's use a Fujitsu gate array implementation of Sun's RISC architecture (SPARC) for the CPU, and then a pair of standard Weitek math chips for floating point. A 2nd gate array controls the Weitek chips & interfaces them to the CPU. Don't know of references, though. 3. You might try digging around in the HP Technical Journal for material on floating-point coprocessors for the Precision (aka Spectrum) architecture. -- -Mark Johnson *** DISCLAIMER: Any opinions above are personal. *** UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark TEL: 408-991-0208 US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
amos@taux01.UUCP (Amos Shapir) (04/17/88)
In article <2038@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: > 1. The IBM PC/RT uses a RISC processor and, I believe, a Motorola > MC68881 for floating point coprocessor. No, it uses NSC's 32081 FPU chip. -- Amos Shapir (My other cpu is a NS32532) National Semiconductor (Israel) 6 Maskit st. P.O.B. 3007, Herzlia 46104, Israel Tel. +972 52 522261 amos%taux01@nsc.com 34 48 E / 32 10 N
wesommer@athena.mit.edu (William Sommerfeld) (04/17/88)
In article <571@taux01.UUCP> amos@taux01.UUCP (Amos Shapir) writes: >In article <2038@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >> 1. The IBM PC/RT uses ... a Motorola >> MC68881 for floating point coprocessor. > >No, it uses NSC's 32081 FPU chip. I claim that you're wrong. The `APC' model PC/RT (the CMOS version which runs at roughly 3-4MIPS, as opposed to the original dog which runs at 1.5MIPS) uses a 68881 FPU; there is also an option for a higher performance `AFPA' unit. When I looked at the AFPA board, it appeared that it used one or more AMD chips which I couldn't identify from memory. The ACIS 4.3BSD for the RT logs the following on reboot: Mar 20 01:33:12 snorkelwacker vmunix: AFPA marked down pending microcode load and initialization. Mar 20 01:33:12 snorkelwacker vmunix: 68881 enabled. By the way, this is being posted from a `slow'-model RT, which is at least marginally faster than a MicroVAX II... Bill Sommerfeld MIT Project Athena. wesommer@athena.mit.edu
tim@amdcad.AMD.COM (Tim Olson) (04/18/88)
In article <571@taux01.UUCP> amos@taux01.UUCP (Amos Shapir) writes: | In article <2038@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: | > 1. The IBM PC/RT uses a RISC processor and, I believe, a Motorola | > MC68881 for floating point coprocessor. | | No, it uses NSC's 32081 FPU chip. The earliest versions of the RT (NMOS processor) had the option of software floating-point or the National chip. The new RT (Faster, CMOS processor) comes standard with the '881. -- Tim Olson Advanced Micro Devices (tim@amdcad.amd.com)
jeff@polyslo.UUCP (Skippy The Wonder Hacker) (04/18/88)
In article <571@taux01.UUCP> amos@taux01.UUCP (Amos Shapir) writes: >In article <2038@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >> 1. The IBM PC/RT uses a RISC processor and, I believe, a Motorola >> MC68881 for floating point coprocessor. > >No, it uses NSC's 32081 FPU chip. Actually you are both right. There are now three types of floating point for the RT: 1) FPA1 - uses 32081 2) FPA2 - uses weitek(I think) 3) New RT processors also have a 68881 on the cpu card Jeff Weinstein Computer Systems Lab Cal Poly State Univ jeff@polyslo.uucp ucbvax!voder!polyslo!jeff
benoni@ssc-vax.UUCP (Charles L Ditzel) (04/18/88)
In article <2038@obiwan.mips.COM>, mark@mips.COM (Mark G. Johnson) writes: > In article <27292@yale-celray.yale.UUCP>, tam-hong@CS.Yale.EDU (Hong Tam) says > > Does anyone know any references about the RISC architecture > > with floating point co-processor? I tried very hard but still > > couldn't find any papers written about it. > > 2. The Sun-4's use a Fujitsu gate array implementation of Sun's RISC > architecture (SPARC) for the CPU, and then a pair of standard > Weitek math chips for floating point. A 2nd gate array controls > the Weitek chips & interfaces them to the CPU. Don't know of > references, though. Actually, Electronic News of March 21 page 23 talks about a "Coprocessor From TI Aimed at SPARC". "The SN74ACT8847 was designed to be used with a number of CISC devices as well...Combining floating point and integer capabilities, the 8847 is said to perform 30 Mflops in single and double precision operations. " I know zero about this...just what I have read...thought i'd pass it on. --------------- My Opinions are naturally my own and in no way should they be attributed to my employer.
sauer@ibmchs.UUCP (Charlie Sauer) (04/19/88)
The current RT Advanced Processor Card includes a 20 MHz 68881 as a floating
point co-processor. There is an optional "Advanced Floating Point Accelerator"
(AFPA) card which uses an ADSP 3221 ALU, 3210 multiplier and 1401 sequencer.
The microcode on the AFPA provides trigonometric and other functions. There is
a gate array that goes between either of these and the ROMP-C fixed point
processor. The gate array presents a 68020-like interface to the 68881 and
presents a DMA-like interface to the ROMP, so that fixed point and floating
point operations can proceed concurrently. I don't know of any externally
available documentation on these other than the Hardware Technical Reference,
SV21-8024. (Orderable at IBM branch offices.)
The original RT processor card has no built in floating point processor.
An FPA for the original processor card is described in Scott M. Smith,
"Floating Point Accelerator" in RT Personal Computer Technology SA23-1057,
January 1986. That FPA uses an NS32081.
AIX provides a DMA-like floating point compatibility interface which is bound
to the process at exec time so that object code can be compiled to be
independent of the floating point hardware. This interface has sufficiently
low overhead that AIX does not provide a direct interface to the 68881. A
direct interface to the AFPA is provided. The compatibility interface is
documented in AIX Operating System Technical Reference Version 2.1, SBOF-0135.
All of the above are designed to be compliant with IEEE P754 10.1.
--
Charlie Sauer IBM AES/ESD, D18/802 uucp: ut-sally!ut-emx!ibmaus!sauer
11400 Burnet Road csnet: ibmaus!sauer@EMX.UTEXAS.EDU
Austin, Texas 78758 aesnet: sauer@auschs
(512) 823-3692 vnet: SAUER at AUSVM6daryl@hpcllcm.HP.COM (Daryl Odnert) (04/19/88)
/ hpcllcm:comp.arch / mark@mips.COM (Mark G. Johnson) / 8:24 am Apr 16, 1988 / > 3. You might try digging around in the HP Technical Journal for > material on floating-point coprocessors for the Precision > (aka Spectrum) architecture. -- See the article titiled "Hewlett-Packard Precision Architecture: The Proecessor" by Michael J. Mahon et. al. in the August 1986 edition of the Hewlett-Packard Journal (Volume 37, No. 8). The article concentrates mainly on the CPU but there is a section that discusses the FPC. Daryl Odnert HP Computer Language Lab hplabs!hpcllcm!daryl
mikep@amdcad.AMD.COM (Mike Parker) (04/21/88)
In article <1863@ssc-vax.UUCP> benoni@ssc-vax.UUCP (Charles L Ditzel) writes: > >Actually, Electronic News of March 21 page 23 talks about a "Coprocessor >From TI Aimed at SPARC". "The SN74ACT8847 was designed to be used with >a number of CISC devices as well...Combining floating point and integer I thought that article was priceless. Early on it cliamed the TI chip was "designed to work with SPARC", then later it said that Cypress was working on an interface chip to connect the TI chip to SPARC. Talk about opportunistic marketing! mikep - my opinions are my own -- ------------------------------------------------------------------------- UUCP: {ucbvax,decwrl,ihnp4,allegra}!amdcad!mike ARPA: amdcad!mike@decwrl.dec.com