ccplumb@lion.waterloo.edu (Colin Plumb) (03/01/90)
In article <10784@june.cs.washington.edu> dgb@cs.washington.edu (David Bradlee) writes: >How long does a double precision multiply really take on the i860? Two pipeline stages, at two clocks per pipeline stage. Thus, four clocks total. Add one for register write. 0 fmul src2, src2, dst0 1 fnop 2 fmul src3, src3, dst1 3 fnop 4 fmul src4, src4, dst2 5 ...result of multiplication is now available... >Also, this must mean that double dual operation instructions (add and multiply) >must be interspersed with fnops to avoid delays, right? (I'm assuming >dual mode here, where we keep the core unit running). Yes. Of course, if you don't need an integer instruction that cycle, you might as well leave out the nop. >One other clarafication on the dual operation instructions. If one of >the special registers (KR,KI,T) is used as an input and loaded by the >same instruction, is the input (to the adder or multiplier) the old >value of that register? I'm not quite clear on what you're asking. If you have one of the instructions where the multiplier feeds to T and T feeds the adder, the adder gets the new value of T. -- -Colin