kjchang@hplabsz.HPL.HP.COM (K. J. Chang) (06/28/89)
I have a couple of questions and I hope someone can enlighten me:
1. when someone says MIPS architecture, does he mean a special kind
of chip architecture or he is from a company called MIPS and
he simply wants to sell its products. I know MIPS also stands
for million instructions per sec.
2. SPARK. What is its definition? Where can I found good references?
Is it related to RISC?
3. RISC. I knew this was a berkeley stuff. Does Stanford have a similar
stuff?
4. CISC. What is its fate? Can I get some good articles on this topic
which are not written by berkeley's risc group |-)?
Thanks for your attention,
-Chang
e-mail: kjchang@hplkjc.hpl.hp.com or
kjchang@hplabsz.hpl.hp.com khb%chiba@Sun.COM (Keith Bierman - SPD Languages Marketing -- MTS) (06/30/89)
In article <3536@hplabsz.HPL.HP.COM> kjchang@hplabsz.UUCP (Jeng Chang) writes: >I have a couple of questions and I hope someone can enlighten me: > >1. when someone says MIPS architecture, does he mean a special kind > of chip architecture or he is from a company called MIPS and > he simply wants to sell its products. I know MIPS also stands > for million instructions per sec. It means: 1) Stanford's MIPS project (now a Darpa standard) Most notable for its ditching interlocks "for performance reasons" 2) The product of MIPSco which has lots of (but not quite enough to avoid mandatory NOPs) interlocks. Both machines have a small flat register file (as opposed to windows (SPARC, BSD RISC and as opposed to AMD29K) >2. SPARK. What is its definition? Where can I found good references? SPARC. Call your local Sun sales office. Or call TI, Cypress, BIT, LSI, or Fujitsu. All have papers, manuals, specs, etc. > Is it related to RISC? Depends on your flavor of religon. Most folks consider SPARC to be as much a RISC as 88K, 29K, MIPSco. Purists might insist that all are much too complicated. I just like to think of them as machines, with many features in common. >3. RISC. I knew this was a berkeley stuff. Does Stanford have a similar > stuff? MIPS was the Stanford "version" of RISC. I refuse to get into arguments about who did RISC first (though when I did, I used to argue Seymour Cray). >4. CISC. What is its fate? Can I get some good articles on this topic > which are not written by berkeley's risc group |-)? > Get the Hot Chips handout. Chat with your local Moto and Intel chip salesman. I'm sure they will explain how much better CISC is. Cheers Keith H. Bierman |*My thoughts are my own. Only my work belongs to Sun* It's Not My Fault | Marketing Technical Specialist ! kbierman@sun.com I Voted for Bill & | Languages and Performance Tools. Opus (* strange as it may seem, I do more engineering now *)
rec@dg.dg.com (Robert Cousins) (06/30/89)
In article <3536@hplabsz.HPL.HP.COM> kjchang@hplabsz.UUCP (Jeng Chang) writes: >I have a couple of questions and I hope someone can enlighten me: >3. RISC. I knew this was a berkeley stuff. Does Stanford have a similar > stuff? The original RISC processors were experiemental and developed independently (more or less) at 1BM, Berkeley and Standford. Today's RISC processors, such as the 88K, define a complete yet general purpose architecture suitable for a wide variety of tasks. These original attempts were designed more for proof of purpose than anything else. >4. CISC. What is its fate? Can I get some good articles on this topic > which are not written by berkeley's risc group |-)? CISC is going strong and most marketing studies show that CISC processors will continue to dominate the market for atleast the next few years. However, if you read the marketing hype you will notice that CISCs are becomming RISCier with each generation. >Thanks for your attention, >-Chang >e-mail: kjchang@hplkjc.hpl.hp.com or > kjchang@hplabsz.hpl.hp.com Robert Cousins Dept. Mgr., Workstation Dev't. Data General Corp. Speaking for myself alone.