les@unicads.UUCP (Les Milash) (09/08/89)
In article <27133@proton.mips.COM> wilkes@mips.COM (John Wilkes) writes: >In article <7851@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes: >doesn't the amd 29000 have external i and d busses? it's been a long time >since i looked at that chip... roger. they share the addr-out bus; they want to emit an i-addr and expect the memory system to stream successive inst's in on its own. also this chip works well with the vram trick, fetching inst's out of the vram's serial port, except it looks like they're gonna be faster than vrams pretty soon; they're already interleaving vrams. V3 Corp (in toronto i think) makes a 1-chip 0-glue dram controller that does all the right stuff, so a minimal system looks like 3 pga's and dram. the chip's got a voracious appetite for memory, but they've done lots of tricks to keep from hitting on the dram. they also have a "branch target cache" so that during a branch they can execute 3 inst's, if your i-mem can start delivering inst's that fast you never have to stall. all in all a clean&fast chip; i love it. (but i haven't seen the RX000 or 88k yet). Requires Investment in Static-ram Computer Les
phil@diablo.amd.com (Phil Ngai) (09/14/89)
In article <624@unicads.UUCP> les@unicads.UUCP (Les Milash) writes: |also this chip works well with the vram trick, fetching inst's out of the |vram's serial port, except it looks like they're gonna be faster than vrams |pretty soon; they're already interleaving vrams. But note that Toshiba's 256K x 4 VRAMs can shift at 25 ns. This can at least take you up to 25 MHz with very little effort. (making the shift clock takes another 7-10 ns) What if someone made a VRAM from SRAM? With a smarter shift clock? -- Phil Ngai, phil@diablo.amd.com {uunet,decwrl,ucbvax}!amdcad!phil "In the West, the only waste of water is not to use it."