holmer@ucbarpa.Berkeley.EDU (Bruce K. Holmer) (05/14/91)
[] I would like any information or references to articles/books concerning the control part of pipelined RISC processors. Kogge (The Architecture of Pipeline Computers, McGraw-Hill 1981) distinguishes two basic types of pipeline control: data stationary and time stationary. He also mentions another variant, modified data stationary. What I would like is a detailed description of the control hardware used in current commercial RISC processors. Block diagrams are helpful, but I would really like to know things like: Is the opcode decoded once-and-for-all immediately after it is fetched and the control signals delayed the necessary amount (depending on which stage of the pipe the control signal goes to)? [this is Kogge's modified data stationary control] Does the opcode pass down its own pipeline and get decoded at each stage of the pipeline (with the possibility of the opcode being modified somewhere down the pipe)? [this is Kogge's data stationary control] There are many other possible variations. Thanks in advance, Bruce Holmer holmer@ucbarpa.berkeley.edu