baum@Apple.COM (Allen J. Baum) (07/19/88)
[] >In article <613@bacchus.DEC.COM> stark@decwrl.UUCP (Don Stark) writes: >In article <9301@dartvax.Dartmouth.EDU> barry.fagin@dartmouth.edu (Barry S. Fagin) writes: >> >>Cache memories, as we all know, typically supply either a memory word or >>an indication of a miss once every CPU clock cycle. For direct-mapped >>caches, the data is available before the hit/miss indication, due to the >>necessity of an associative comparison. My question is the following: >>why not provide the datum to the CPU as soon as it is available, and >>delay the miss indication till the next clock cycle? The DEC Multi-Titan did this, on the assumption that the loss in performance caused by direct mapped vs. set assoc. would be offset by the gain in speed andsimplicity of direct mapped. The was a paper at the June 88 Comp Arch. Symp. that described the parameters of when this makes sense. -- {decwrl,hplabs,ihnp4}!nsc!apple!baum (408)973-3385