[comp.arch] Even Bigger RISC Bibliography

papowell@umn-cs.UUCP (Patrick Powell) (03/05/87)

Whoo Boy! I got quite a few replies to my original request for RISC
bibliographies, but I never expected the second wave. I have combined
them into a new bibliography; I am posting the combination rather than
a set of diff's.

If you have some that I missed, or have corrected entries, please mail
them to me and I will update as required.

Patrick Powell
#! /bin/sh
# This is a shell archive, meaning:
# 1. Remove everything above the #! /bin/sh line.
# 2. Save the resulting text in a file.
# 3. Execute the file with /bin/sh (not csh) to create:
# RISC
# This archive created: Thu Mar 5 09:40:33 1987
export PATH; PATH=/bin:/usr/bin:$PATH
if test -f 'RISC'
then
echo shar: "will not over-write existing file 'RISC'"
else
cat << \SHAR_EOF > 'RISC'

%T RIDGE 32 Architecture \(em a RISC Variation
%l proceedings-article
%A E. Basart
%A D. Folger
%C Port Chester, New York
%D 1983
%J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Oct

%T Understanding Execution Behaviour of Software Systems
%l journal-article
%A J. C. Browne
%D 1984
%J Computer
%K risc reduced instruction set computer restricted architecture
%N 7
%V 17

%T u3L: An HLL-RISC Processor for Parallel Execution of FP-Language Programs
%l proceedings-article
%A M. Castran
%A R. P. Organick
%D 1982
%J Proc Ninth Annual Symp on Computer Architecture
%K RISC
%M April
%P 239-247

%T Comments on 'The Case for the Reduced Instruction Set Computer'
%l journal-article
%A D. W. Clark
%A W. D. Strecker
%D 1980
%J Computer Architecture News
%K risc reduced instruction set computer restricted architecture
%M Oct
%V 8

%T Fewer Instructions Speed Up VLSI
%l journal-article
%A B. Clifford
%D 1982
%J Electronics
%K RISC
%M November
%N 23
%P 101-102
%V 55

%T A Perspective on the Processor Complexity Controversy
%l proceedings-article
%A R. P. Colwell
%A C. Y. Hitchcock III
%A E. D. Jensen
%C Port Chester, New York
%D 1983
%J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Oct
%P 613-616

%T Peering through the RISC/CISC Fog: An Outline of Research
%l journal-article
%A R. P. Colwell
%A C. Y. Hitchcock III
%A E. D. Jensen
%D 1983
%I ACM
%J Computer Architecture News
%K archons 432 object-oriented overlapped multiple register sets
%M March
%N 1
%P 44-50
%V 11
%X attempt to determine if RISCs faster than CISCs, and why

%T Computer Architecture: Some Old Ideas that Haven't Quite Made It Yet
%l journal-article
%A P. J. Denning
%D 1981
%J CACM
%K RISC
%M September
%N 9
%P 553-554
%V 24

%T Altering Computer Architecture is a Way to Raise Throughput Suggests IBM Researchers
%l journal-article
%A Electronics
%D 1976
%J Electronics
%K RISC
%M December
%N 25
%P 30-31
%V 49

%T Very Long Instruction Word Architectures and the ELI 512
%l proceedings-article
%A J. A. Fisher
%D 1983
%J Int. Symp. on Computer Architecture
%K parallel data flow trace scheduling cray-1 RISC multiprocessor
%P 140

%T A RISCy Approach to VLSI
%l journal-article
%A D. T. Fitzpatrick
%A J. K. Foderaro
%A M. G. H. Katevenis
%A H. A. Landman
%A D. A. Patterson
%A J. B. Peek
%A Z. Peshkess
%A C. H. Sequin
%A R. W. Sherbourne
%A K. S. Van Dyke
%D 1981
%J VLSI Design
%K risc reduced instruction set computer architecture restricted
%N 4th Quarter

%T Running RISCs
%l journal-article
%A J. K. Foderaro
%A K. S. Van Dyke
%A D. A. Patterson
%D 1982
%J VLSI Design
%K risc reduced instruction set computer architecture restricted
%N September/October

%T A Perspective on High-Level Language Architecture (extended abstract)
%l proceedings-article
%A Thomas Gross
%A John Hennessy
%A Norman Jouppi
%A Steven Przybylski
%A Christopher Rowen
%A Anant Agarwal
%A Peter Steenskiste
%D 1984
%I Univ. of Maryland
%J International Workshop on High-Level Computer Architecture
%K risc reduced instruction set computer restricted architecture
%M May

%T A Performance Evaluation of the Intel iAPX432
%l journal-article
%A Hansen
%A Mayo
%A Linton
%A Murphy
%A Patterson
%D 1982
%J Computer Architecture News
%K risc reduced instruction set computer architecture restricted
%M June
%X bench marks the 432 on the same test programs used to test RISC

%T Re-Evaluation of RISC 1
%l journal-article
%A J. L. Heath
%D 1984
%J Computer Architecture News
%K reduced instruction set computer benchmarks 68000 16000
%M March
%N 1
%P 3-10
%V 12
%X comparison of performance

%T Hardware/Software Tradeoffs for Increased Performance
%l manuscript
%A J. Hennessy
%A N. Jouppi
%A F. Baskett
%A T. Gross
%A J. Gill
%K risc reduced instruction set computer restricted architecture
%O unknown publication

%T MIPS: A VLSI Processor Architecture
%l book-article
%e G. Steele
%A J. Hennessy
%A N. Jouppi
%A F. Baskett
%A J. Gill
%B VLSI Systems and Computations
%D 1981
%E H. T. Kung
%E R. Sproull
%I Computer Science Press
%K pipelines delayed branch jump reduced instruction set computer risc
%P 337-346

%T MIPS: A VLSI Processor Architecture
%l proceedings-article
%A J. Hennessy
%A et al
%D 1981
%J Proc of the CMU Conference on VLSI systems And Computations
%K RISC
%M October
%P 337-346

%T The MIPS Machine
%l proceedings-article
%A J. Hennessy
%A et al
%D 1982
%J Proceedings of COMPCON Spring 82
%K RISC
%M February
%P 2-7

%T MIPS: A Microprocessor Architecture
%l proceedings-article
%A J. Hennessy
%A N. Jouppi
%A S. Przybylski
%A C. Rowen
%A T. Gross
%A F. Baskett
%A J. Gill
%D 1982
%J 15th Ann. Workshop on Microprogramming
%K risc reduced instruction set computer architecture restricted
%M November
%P 17-22

%T Performance Issues in VLSI Processor Design
%l proceedings-article
%A J. Hennessy
%A N. Jouppi
%A S. Przybylski
%A C. Rowen
%A T. Gross
%C Port Chester, New York
%D 1983
%J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Oct
%P 153-156

%T A Definition of RISC
%l proceedings-article
%A Martin E. Hopkins
%D 1984
%I Univ. of Maryland
%J International Workshop on High-Level Computer Architecture
%K risc reduced instruction set computer restricted architecture
%M May
%P 8-11
%X Tries to definite RISCs in the IBM 801 context in comparison to the IBM 370

%T HLLDA Defies RISC: Thoughts on RISCs, CISCs, and HLLDAs
%l proceedings-article
%A W. C. Hopkins
%C Downingtown, Pa.
%J MICRO 16, Proc. 16th Annual Microprogramming Workshop
%M Oct
%Y 1983

%T The RISC II Micro-Architecture
%l journal-article
%A M. G. H Katevenis
%A R. W Sherburne
%A D. A. Patterson
%A C. H. Sequin
%D 1983
%J VLSI 83
%K risc reduced instruction set computer architecture restricted
%M August

%T Reduced Instruction Set Computer Architectures for VLSI
%l dissertation
%A M. G. H. Katevenis
%C Berkeley, CA 94720
%D 1983
%I University of California
%K risc reduced instruction set computer architecture
%S Computer Science Division
%X This is the Ph. D. thesis written by one of the designers of the RISC I & II.
There is a nice summary of the RISC project, the rationale behind
it, and implementation details of the RISC II chip.

%T A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I
%l journal-article
%A J. R. Larus
%D 1982
%J Computer Architecture News
%K risc reduced instruction set computer architecture restricted
%M September
%N 5
%P 10-15
%V 10

%T A Small, High-speed Dataflow Processor
%l proceedings-article
%A W. Leler
%A H. J. Siegel
%A L. Siegel
%C Bellarire, MI.
%D 1983
%J Proc. 1983 Conf. on Parallel Processing
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Aug

%T An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints
%l journal-article
%A Yuh-Zen Liao
%A C. K. Wong
%D 1983
%J IEEE Trans. on Computer Aided Design
%K risc reduced instruction set computer restricted architecture
%M April
%N 2
%V CAD-2

%T RISC Chips
%l journal-article
%A J. Markoff
%D 1984
%J Byte
%K RISC
%M November
%N 12
%P 191-206
%V 9

%T IBM Mini a Radical Departure
%l journal-article
%A V. McLellan
%D 1979
%J Datamation
%K RISC
%M October
%N 11
%P 53-55
%V 25

%T Internal Floating-point Processor Further Boosts RISC Machine Speed
%l journal-article
%A S. Ohr
%D 1984
%J Electronics Design
%K risc reduced instruction set computer restricted architecture
%N 18
%V 32

%T Tradeoffs in the design of a system for high level language interpretation
%l proceedings-article
%A F. C. C. Osorio
%A Y. N. Patt
%D 1983
%J Proc. Intl. Conf. on Computer Design (ICCD)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Oct

%T The Case for the Reduced Instruction Set Computer
%l journal-article
%A D. A. Patterson
%A D. R. Ditzel
%D 1980
%J Computer Architecture News
%K risc reduced instruction set computer restricted architecture
%M Oct
%V 8

%T RISC 1 : A Reduced Instruction Set VLSI Computer
%l proceedings-article
%A D. A. Patterson
%A C. H. Sequin
%D 1981
%J 8th. Ann. Symp. on Computer Architecture
%K risc reduced instruction set computer restricted architecture
%M May

%T RISC Assessment: A High-Level Language Experiment
%l proceedings-article
%A D. A. Patterson
%A R. S. Piepho
%D 1982
%J 9th Symp. on Computer Architecture
%K risc reduced instruction set computer architecture restricted
%M April
%P 3-8

%T A VLSI RISC
%l journal-article
%A D. A. Patterson
%A C. H. Sequin
%D 1982
%J Computer
%K risc reduced instruction set computer architecture restricted
%M September
%N 9
%P 8-21
%V 15

%T A RISCy APPROACH TO COMPUTER DESIGN
%l proceedings-article
%A D. A. Patterson
%D 1982
%I IEEE Computer Society press
%J COMPCON
%K risc reduced instruction set computer architecture restricted
%M Spring
%P 8-14

%T Architecture of a VLSI Instruction Cache for a RISC
%l proceedings-article
%A D. A. Patterson
%A P. Garrison
%A M. Hill
%A D. Lioupis
%A C. Nyberg
%A T. Sippel
%A K. Van Dyke
%D 1983
%J Int. Symp. on Computer Architecture
%K fault tolerance associative memory SAMOS
remote program counter jump branch likely bit
%P 108

%T RISC Watch
%l journal-article
%A D. A. Patterson
%D 1984
%J Computer Architecture News
%K reduced instruction set computer benchmarks
%M March
%N 1
%P 11-19
%V 12

%T The 801 Minicomputer
%l journal-article
%A G. Radin
%D 1983
%J IBM J. Res. Dev.
%K RISC computer architecture IBM 801 cache
%N 3
%P 237
%V 27

%T A Reduced High-Level-Language Instruction Set
%l journal-article
%A P. U. Schultess
%D 1984
%J Micro
%K descriptor based addressing stack architecture reduced instruction set
computer risc language directed
%M June
%N 3
%P 55-67
%V 4

%T OPA - A New Architecture for Pascal-Like Languages
%l journal-article
%A P. Schulthess
%A F. Vonaesch
%D 1982
%J ACM Computer Architecture News
%K stack RISC language directed
%M Dec
%N 6
%P 9
%V 10

%T Design and Implementation of RISC I
%l book-article
%A C. H. Sequin
%A D. A. Patterson
%K computer architecture register testing
%P 276-298

%T Local Memory In RISCs
%l proceedings-article
%A R. W. Sherburne
%A M. Katenvenis
%A D. A. Patterson
%A C. H. Sequin
%C Port Chester, New York
%D 1983
%J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Oct

%T The RISC II Micro-architecture
%l proceedings-article
%A R. W. Sherburne
%A M. Katenvenis
%A D. A. Patterson
%A C. H. Sequin
%D 1983
%J Proc. Intl. Conf. on Computer Design (ICCD)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M Oct

%T MOVE Architecture in Digital Computers
%l journal-article
%A Daniel Tabak
%A G. J. Lipovski
%D 1980
%J IEEE Trans. on Computers
%K RISC CMOVE architecture
%M February
%N 2
%P 180-189
%V C-29

%T Strategies for Managing the Register File in RISC
%l journal-article
%A Y. Tamir
%A C. H. Sequin
%D 1983
%J IEEE Trans. on Computers
%K risc reduced instruction set computer restricted architecture
%M Nov

%T Architecture of SOAR: Smalltalk on a Risc
%l proceedings-article
%A D. Ungar
%A R. Blau
%A P. Foley
%A D. Samples
%A D. Patterson
%D 1984
%I SIGARCH
%J 11th Annual International Symposium on Computer Architecture
%K object oriented architectures reduced instruction set architectures
tagged object oriented architectures garbage collection
%P 188-197

%T A Language-Oriented Approach for Implementing Branches: Structured
Control Flow
%l proceedings-article
%A Robert G. Wedig
%D 1984
%I Univ. of Maryland
%J International Workshop on High-Level Computer Architecture
%K risc reduced instruction set computer restricted architecture
%M May

%T Keeping Jump Instructions out of the Pipeline of a RISC-Like Computer
%l journal-article
%A M. V. Wilkes
%D 1983
%I ACM
%J Computer Architecture News
%M Dec
%N 5
%P 5-7
%V 11

%l technical-report
%A R. H. Katz
%A S. J. Eggers
%A G. A. Gibson
%A P. M. Hansen
%A M. D. Hill
%A J. M. Pendleton
%A S. A. Ritchie
%A G. S. Taylor
%A D. A. Wood
%A D. A. Patterson
%T Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses
%R UCB/CSD 85/221
%Y UCB85
%I Computer Science Division (EECS),
University of California, Berkeley
%M January
%D 1985
%K RISC Architecture,
Tightly Compled Multiprocessor, Memory Hierarchy, Cache Design
%X
We describe the memory system design of a tightly-coupled multiprocessor.
Each
processor node consists of a VLSI RISC processor,
a VLSI cache controller,
cache data RAMS,
and a standard bus.
We show that adequate performance can be
achieved only if the processor has an on-chip instruction buffer and a large
(64KB to 256KB) local instruction and data cache.

%T SPUR: A VLSI Multiprocessor Workstation
%l technical-report
%A M.D. Hill
%A S. J. Eggers
%A J. R. Larus
%A D. A. Hodges
%A R. H. Katz
%A J. Ousterhout
%A D. A. Patterson
%a et al
%C Berkeley
%D 1985
%I Computer Science Division, University of California
%K address translation, cache, cache consistency, IEEE floating-point,
Lisp, multiprocessor, RISC, shared-bus, tagged architecture
%M December
%P 27
%R UCB/CSD 86/273
%X SPUR (Symbolic Processing Using RISCs) is a workstation for conducting
parallel processing research. SPUR conatins 6 to 12 high-performance
homogenous processors connected with a shared bus. The number of processors
is large enough to permit parallel processing experiments, but small
enough to allow packaging as a personal workstation.

%T An Overview of the PL.8 Compiler
%l proceedings-article
%A Marc Auslander
%A Martin Hopkins
%D 1982
%J Proc. of the Sigplan 82 Symp. on Compiler Construction
%M June
%P 22-31
%X The language and compiler of the IBM 801.
These proceedings appear as Sigplan Notices, vol. 17, no. 6.
%K risc reduced instruction set computer restricted architecture

%T The MODHEL Microcomputer for RISCs Study
%l journal-article
%A H. Azaria
%A D. Tabak
%D 1983
%J Microprocessing and Microprogramming
%M October-November
%K risc reduced instruction set computer restricted architecture

%T Fewer instructions speed up VLSI
%l journal-article
%A Clifford Barney
%D 1982
%J Electronics
%M November 17
%N 23
%P 101-102
%V 55
%X Short article about RISC processors. Good photo of RISC I die.
%K risc reduced instruction set computer restricted architecture

%T RISC supermini has stellar perfomance
%l journal-article
%A Clifford Barney
%D 1983
%J Electronics
%M August 11
%P 149-150
%X Brief description of the Pyramid 90x.
%K risc reduced instruction set computer restricted architecture

%T RISC: Is it a Good Idea or Just Another Hype?
%l journal-article
%A Clifford Barney
%A Tom Manuel
%D 1986
%J Electronics
%M May 5
%N 18
%P 28-31
%V 59
%K risc reduced instruction set computer restricted architecture

%T RISC Design Streamlines High-Power CPUs
%l journal-article
%A E. Basart
%D 1986
%J Computer Design
%M July
%K risc reduced instruction set computer restricted architecture

%T Ridge 32 Architecture -- A RISC Variation
%l journal-article
%A Ed Basart
%A Dave Folger
%D 1983
%J ICCD 83
%M October
%P 315-318
%K risc reduced instruction set computer restricted architecture

%T RISC Design Streamlines High-power CPUs
%l journal-article
%A Ed Basart
%D 1985
%J Computer Design
%M July 1
%P 119-122
%K risc reduced instruction set computer restricted architecture

%T RISC: Back To The Future?
%l journal-article
%A C. Bell
%D 1986
%J Datamation
%M June
%K risc reduced instruction set computer restricted architecture

%T RISCs -- Reduced Instruction Set Computers -- Make Leap
%l journal-article
%A R. Bernhard
%D 1984
%J Systems and Software
%M December
%K risc reduced instruction set computer restricted architecture

%T More Hardware Means Less Software
%l journal-article
%A Robert Bernhard
%D 1981
%J IEEE Spectrum
%M December
%N 12
%P 30-37
%V 18
%K risc reduced instruction set computer restricted architecture

%T IBM's 'Secret Computer' - A New Angle in Software
%l journal-article
%A Robert Bernhard
%D 1983
%J Systems & Software
%M August
%P 51-52
%K risc reduced instruction set computer restricted architecture

%T Beyond RISC: High-Precision Architecture
%l proceedings-article
%A J. Birnbaum
%A W. Worley
%D 1986
%J Proceedings, Compcon Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T Beyond RISC: High-Precision Architecture
%l journal-article
%A Joel S. Birnbaum
%A William S. Worley, Jr.
%D 1985
%J Hewlett-Packard Journal
%M August
%N 8
%P 4-10
%V 36
%X The architectural design of Hewlett-Packard's next generation of computers.
%K risc reduced instruction set computer restricted architecture

%T A Big RISC
%l technical-report
%A R. Blomseth
%D 1983
%I U. C. Berkeley
%M November
%R Computer Science Technical Report UCB/CSD 83/143
%K risc reduced instruction set computer restricted architecture

%T A Microprocessor Design Using the Yorktown Silicon Compiler
%l journal-article
%A R. K. Brayton
%A C. L. Chen
%A G. De Micheli
%A R. H. J. M. Otten
%A J. Katzenelson
%A C. T. McMullen
%A R. L. Rudell
%D 1985
%J ICCD 85
%M October
%P 225-231
%X The IBM 801 in (compiled) silicon.
%K risc reduced instruction set computer restricted architecture

%T Understanding Execution Behavior of Software Systems
%l journal-article
%A J. Browne
%D 1984
%J Computer
%M July
%K risc reduced instruction set computer restricted architecture

%T The RISC Factor
%l journal-article
%A C. Bruno
%A S. Brady
%D 1986
%J Datamation
%M June
%K risc reduced instruction set computer restricted architecture

%T Building Blocks Yield Fast 32-Bit RISC Machines
%l journal-article
%A B. Case
%D 1985
%J Computer Design
%M July
%K risc reduced instruction set computer restricted architecture

%T Building Blocks Yield Fast RISC 32-bit RISC Machines
%l journal-article
%A Brian Case
%D 1985
%J Computer Design
%M July 1
%P 111-117
%X How the AMD 29300 family could be used in a RISC machine.
%K risc reduced instruction set computer restricted architecture

%T Register Allocation and Spilling via Graph Coloring
%l proceedings-article
%A G. Chaitin
%D 1982
%J Proc. SIGPLAN Symp. Compiler Construction
%M June
%K risc reduced instruction set computer restricted architecture

%T Engineering a RISC Compiler System
%l proceedings-article
%A F. Chow
%A M. Himelstein
%A E. Killian
%A L. Weber
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T Engineering a RISC Compiler System
%l journal-article
%A F. Chow
%A M. Himelstein
%A E. Killian
%A L. Weber
%D 1986
%J Compcon Spring 86
%M March
%P 132-137
%K risc reduced instruction set computer restricted architecture

%T Comments on 'The Case for the Reduced Instruction Set Computer'
%l journal-article
%A Douglas W. Clark
%A William D. Strecker
%D 1980
%J Computer Architecture News
%K risc reduced instruction set computer restricted architecture
%M October
%N 6
%P 34-38
%V 8
%K risc reduced instruction set computer restricted architecture

%T Measurement and Analysis of Instruction Use in the Vax-11/780
%l proceedings-article
%A Douglas W. Clark
%A Henry M. Levy
%D 1982
%J Proceedings of the Ninth Annual Symposium on Computer Architecture
%M April
%P 9-17
%K risc reduced instruction set computer restricted architecture

%T Computers, Complexity, and Controversy
%l journal-article
%A R. Colwell
%A C. Hitchcock
%A E. Jensen
%A L. Weber
%D 1985
%J Computer
%M September
%K risc reduced instruction set computer restricted architecture

%T Peering Through the RISC/CISC Fog: An Outline for Research
%l journal-article
%A Robert P. Colwell
%A Charles Y. Hitchcock\0III
%A E. Douglas Jensen
%D 1983
%J Computer Architecture News
%M March
%N 1
%P 44-50
%V 11
%K risc reduced instruction set computer restricted architecture

%T A Perspective on the Processor Complexity Controversy
%l journal-article
%A Robert P. Colwell
%A Charles Y. Hitchcock\0III
%A E. Douglas Jensen
%D 1983
%J ICCD 83
%M October
%P 613-616
%K risc reduced instruction set computer restricted architecture

%T Computers, Complexity, and Controversy
%l journal-article
%A Robert P. Colwell
%A Charles Y. Hitchcock\0III
%A E. Douglas Jensen
%A H. M. Brinkley Sprunt
%A Charles P. Kollar
%D 1985
%J Computer
%M September
%N 9
%P 8-19
%V 18
%X Response and counter\-response to this paper appear in Computer,
vol. 18, no. 11 and 12, November and December 1985.
%K risc reduced instruction set computer restricted architecture

%T Compilers for the New Generation of Hewlett-Packard Computers
%l proceedings-article
%A D. Coutant
%A C. Hammond
%A J. Kelley
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T Compilers for the New Generation of Hewlett-Packard Computers
%l journal-article
%A Deborah S. Coutant
%A Carol L. Hammond
%A Jon W. Kelley
%D 1986
%J Hewlett-Packard Journal
%M January
%N 1
%P 4-18
%V 37
%K risc reduced instruction set computer restricted architecture

%T The Elements of Single Chip Microcomputer Architecture
%l journal-article
%A Harvey G. Cragon
%D 1980
%J Computer
%M October
%N 10
%P 27-41
%V 13
%K risc reduced instruction set computer restricted architecture

%T Microprocessor Architecture Which Reflects Software Requirements
%l journal-article
%A Harvey G. Cragon
%D 1981
%J Compcon Spring 81
%M February
%P 36-39
%K risc reduced instruction set computer restricted architecture

%T A Broader Range of Possible Answers to the Issues Raised by RISC
%l proceedings-article
%A E. Davidson
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T Operating System Support on a RISC
%l proceedings-article
%A M. DeMoney
%A J. Moore
%A J. Mashey
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T Operating System Support on a RISC
%l journal-article
%A M. DeMoney
%A J. Moore
%A J. Mashey
%D 1986
%J Compcon Spring 86
%M March
%P 138-143
%K risc reduced instruction set computer restricted architecture

%T Retrospective on High-Level Computer Architecture
%l proceedings-article
%A David R. Ditzel
%A David A. Patterson
%D 1980
%J Proc. Seventh Annual Symp. on Computer Architecture
%M October
%P 97-104
%K risc reduced instruction set computer restricted architecture

%T Register Allocation for Free: The C Machine Stack Cache
%l proceedings-article
%A David R. Ditzel
%A H. R. McLellan
%D 1982
%J Proc. Symp. Architectural Support of Programming Languages and Operating Systems
%M March
%P 48-56
%X This conference proceedings was also issued as Sigplan Notices,
vol. 14, no. 4, April 1982 and Computer Architecture News, vol. 10,
no. 2, March 1982.
%K risc reduced instruction set computer restricted architecture

%T Altering computer architecture is way to raise throughput, suggests IBM researchers
%l journal-article
%A Electronics
%D 1976
%J Electronics
%M December 23
%N 25
%P 30-31
%V 49
%K risc reduced instruction set computer restricted architecture

%T At 3 MIPS, RISC Processor is Among Fastest Chips Around
%l journal-article
%A Electronics
%D 1985
%J Electronics
%M August 26
%N 34
%P 48-49
%V 58
%X The Acorn RISC Machine.
%K risc reduced instruction set computer restricted architecture

%T Very Long Instruction Word Architectures and the ELI 512
%l journal-article
%A J. A. Fischer
%D 1983
%J Int. Symp. on Computer Architecture
%P 140
%K risc reduced instruction set computer restricted architecture

%T Running RISCs
%l journal-article
%A John K. Foderaro
%A Korbin S. Van\0Dyke
%A David A. Patterson
%D 1982
%J VLSI Design
%K risc reduced instruction set computer architecture restricted
%M September-October
%N September/October
%P 27-32
%V 3
%K risc reduced instruction set computer restricted architecture

%T Computer Architecture - Designing for Speed
%l journal-article
%A David Folger
%A Ed Basart
%D 1983
%J Compcon Spring 83
%M February
%P 25-31
%X Brief description of the Ridge ThirtyTwo.
%K risc reduced instruction set computer restricted architecture

%T Reduced Instruction Set Multi-Microcomputer System
%l proceedings-article
%A L. Foti
%D 1984
%J Proceedings, National Computer Conference
%K risc reduced instruction set computer restricted architecture

%T Back-to-Basics Computers with Sports-Car-Speed
%l journal-article
%A S. Gannes
%D 1985
%J Fortune
%M Deptember
%K risc reduced instruction set computer restricted architecture

%T Back-To-Basics Computers With Sports-Car Speed
%l journal-article
%A Stuart Gannes
%D 1985
%J Fortune
%M September 30
%N 7
%P 98-101
%V 112
%K risc reduced instruction set computer restricted architecture

%T Simple Systems Approach Increases Throughput
%l journal-article
%A P. Goodrich
%D 1985
%J Mini-Micro Systems
%M May
%K risc reduced instruction set computer restricted architecture

%T Floating-Point Arithmetic on a Reduced-Instruction-Set
%l proceedings-article
%A T. Gross
%D 1985
%J Proc., 7th Symp. on Computer Architecture
%K risc reduced instruction set computer restricted architecture

%T Code Optimization of Pipeline Constraints
%l technical-report
%A Thomas Gross
%C Stanford, California 94305
%D 1983
%I Stanford University
%M December
%R Ph.D. Thesis, Stanford University Computer Systems Laboratory, Tech. Report No. 83-255
%K risc reduced instruction set computer restricted architecture

%T A Perspective on High-Level Language Architecture (Extended Abstract)
%l journal-article
%A Thomas Gross
%A John Hennessy
%A Norman Jouppi
%A Steven Przybylski
%A Christopher Rown
%A Anant Agarwal
%A Peter Steenskiste
%D 1984
%J Int'l Workshop on High-Level Computer Architecture
%M May
%K risc reduced instruction set computer restricted architecture

%T Optimizing Delayed Branches
%l proceedings-article
%A Thomas R. Gross
%A John L. Hennessy
%D 1982
%J MICRO 15, Proc. 15th Annual Workshop on Microprogramming
%M October
%P 114-120
%K risc reduced instruction set computer restricted architecture

%T Code Optimization Techniques for Pipelined Architectures
%l journal-article
%A Thomas R. Gross
%D 1983
%J Compcon Spring 83
%P 278-285
%K risc reduced instruction set computer restricted architecture

%T Chip Architecture: a revolution brewing
%l journal-article
%A Fred Guterl
%D 1983
%J IEEE Spectrum
%M July
%N 7
%P 30-37
%V 20
%K risc reduced instruction set computer restricted architecture

%T Re-evaluation of the RISC I
%l journal-article
%A J. L. Heath
%D 1984
%J Computer Architecture News
%M March
%N 1
%P 3-10
%V 12
%K risc reduced instruction set computer restricted architecture

%T VLSI RISC Processors
%l journal-article
%A John Hennesey
%D 1985
%J VLSI Systems Design
%M October
%N 10
%P 22-32
%V VI
%K risc reduced instruction set computer restricted architecture

%T MIPS: A VLSI Processor Architecture
%l book-article
%d November 1981
%e G. Steele
%i Stanford University Technical Report 223
%p 1-11
%A J. Hennessy
%A N. Jouppi
%A F. Baskett
%A J. Gill
%B VLSI Systems and Computations
%D 1981
%E H. T. Kung
%E R. Sproull
%I Computer Science Press
%K MIPS, RISC,
pipelines delayed branch jump reduced instruction set computer,
%P 337-346
%X MIPS is a new single chip VLSI processor architecture. It attempts
to achieve high performance with the use of a simplified instruction
set, similar to those found in microengines. The processor is a fast
pipelined engine without pipeline interlocks.
%K risc reduced instruction set computer restricted architecture

%T MIPS: A VLSI Processor Architecture
%l proceedings-article
%A J. Hennessy
%A et al
%D 1981
%J Proc of the CMU Conference on VLSI systems And Computations
%K RISC
%M October
%P 337-346
%K risc reduced instruction set computer restricted architecture

%T MIPS: A VLSI Processor Architecture
%l book
%A J. Hennessy
%A N. Jouppi
%A F. Baskett
%A J. Gill
%B Proc. CMU Conference on VLSI Systems and Computations
%D 1981
%E H. T. Kung, R. Sproull, and G. Steele
%I Computer Science Press
%P 337-346
%K risc reduced instruction set computer restricted architecture

%T The MIPS Machine
%l proceedings-article
%A J. Hennessy
%A et al
%D 1982
%J Proceedings of COMPCON Spring 82
%K RISC
%M February
%P 2-7
%K risc reduced instruction set computer restricted architecture

%T Performance Issues in VLSI Processor Design
%l proceedings-article
%A J. Hennessy
%A N. Jouppi
%A S. Przybylski
%A C. Rowen
%A T. Gross
%D 1983
%J Proc. Intl. Conf. on Computer Design (ICCD)
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%P 153-156
%K risc reduced instruction set computer restricted architecture

%T Postpass Code Optimization of Pipeline Constraints
%l journal-article
%A J. Hennessy
%A T. Gross
%D 1983
%J ACM Transactions on Programming Languages and Systems
%M July
%K risc reduced instruction set computer restricted architecture

%T Design of a High Performance VLSI Processor
%l book
%A J. Hennessy
%A N. Jouppi
%A S. Przbylski
%A C. Rowen
%A T. Gross
%B Proc. of the Third Caltech Conf. on VLSI
%D 1983
%E Randal Bryant
%I Computer Science Press
%M March
%P 33-54
%K risc reduced instruction set computer restricted architecture

%T VLSI Processor Architecture
%l journal-article
%A J. Hennessy
%D 1984
%J IEEE Transactions on Computers
%M December
%K risc reduced instruction set computer restricted architecture

%T VLSI processor architecture
%l journal-article
%A J. L. Hennessy
%D 1984
%J IEEE Trans. Comput.
%M December
%N 12
%V C-33
%K risc reduced instruction set computer restricted architecture

%T The MIPS Machine
%l journal-article
%A John Hennessy
%A Norman Jouppi
%A John Gill
%A Forest Baskett
%A Alex Strong
%A Thomas Gross
%A Chris Rowen
%A Judson Leonard
%D 1982
%J Compcon Spring 82
%M February
%P 2-7
%K risc reduced instruction set computer restricted architecture

%T Code Generation and Reorganization in the Presence of Pipeline Constraints
%l journal-article
%A John Hennessy
%A Thomas R. Gross
%D 1982
%J Ninth Annual Symp. Principles of Programming Languages
%M January
%P 120-127
%K risc reduced instruction set computer restricted architecture

%T Hardware/Software Tradeoffs for Increased Performance
%l proceedings-article
%A John Hennessy
%A Norman Jouppi
%A Forest Baskett
%A Thomas Gross
%A John Gill
%D 1982
%J Proc. Symp. Architectural Support for Programming Languages
%M March
%P 2-11
%K risc reduced instruction set computer restricted architecture

%T MIPS: A Microprocessor Architecture
%l proceedings-article
%A John Hennessy
%A Norman Jouppi
%A Steven Przybylski
%A Chris Rowen
%A Thomas Gross
%A Forest Baskett
%A John Gill
%D 1982
%J MICRO 15, Proc. 15th Annual Workshop on Microprogramming
%M October
%P 17-22
%X An earlier version of this report , entitled 'MIPS: A VLSI Processor
Architecture' appears in the Proc. of the CMU Conference on VLSI Systems
and Computations, October 1981.
%K risc reduced instruction set computer restricted architecture

%T Postpass Code Optimization of Pipeline Constraints
%l journal-article
%A John Hennessy
%A Thomas Gross
%D 1983
%J ACM TOPLAS
%M July
%N 3
%V 5
%K risc reduced instruction set computer restricted architecture

%T Performance Issues in VLSI Processor Design
%l journal-article
%A John Hennessy
%A Norman Jouppi
%A Steven Przybylski
%A Christopher Rowen
%A Thomas Gross
%D 1983
%J ICCD 83
%M October
%P 153-156
%K risc reduced instruction set computer restricted architecture

%T Origins of an Architecture: 801/RISC
%l journal-article
%A IBM Research Highlights
%D 1986
%J IBM Research Highlights
%N 1
%K risc reduced instruction set computer restricted architecture

%T Experimental Evaluation of On-Chip Microprocessor Cache Memories
%l journal-article
%A Mark D. Hill
%A Alan Jay Smith
%D 1984
%J 11th Annual International Symposium on Computer Architecture
%M June
%P 158-166
%K risc reduced instruction set computer restricted architecture

%T IBM RISC Workstation Features 40-Bit Virtual Addressing
%l journal-article
%A H. Hinden
%D 1986
%J Computer Design
%M February
%K risc reduced instruction set computer restricted architecture

%T Analyzing Multiple Register Sets
%l journal-article
%A C. Hitchcock
%A H. Brinkley
%D 1985
%J 12th Symp. on Computer Architecture
%M June
%K risc reduced instruction set computer restricted architecture

%T A Perspective on Microcode
%l journal-article
%A Martin E. Hopkins
%D 1983
%J Compcon Spring 83
%M February
%P 108-110
%K risc reduced instruction set computer restricted architecture

%T A Defintion of RISC
%l journal-article
%A Martin E. Hopkins
%D 1984
%J Int'l Workshop on High-Level Computer Architecture
%M May
%K risc reduced instruction set computer restricted architecture

%T HLLDA Defies RISC: Thoughts on RISCs, CISCs, and HLLDAs
%l journal-article
%A W. Hopkins
%D 1983
%J 16th Symp. on Microprogramming
%M December
%K risc reduced instruction set computer restricted architecture

%T HP Precision Architecture: The Input/Output System
%l journal-article
%A David V. James
%A Stephen G. Burger
%A Robert D. Odineal
%D 1986
%J Hewlett-Packard Journal
%M August
%N 8
%P 23-30
%V 37
%K risc reduced instruction set computer restricted architecture

%T The RISC II Micro-Architecture
%l journal-article
%A M. G. H. Katevenis
%A R. W. Sherburne
%A D. A. Patterson
%A C. H. Sequin
%C Trondheim, Norway
%D 1983
%J VLSI 83
%K risc reduced instruction set computer architecture restricted
%M August 16-19
%K risc reduced instruction set computer restricted architecture

%T Reduced Instruction Set Computer Architectures for VLSI
%l dissertation
%A Manolis G. H. Katevenis
%C Berkeley, CA 94720
%D 1983
%I University of California
%K risc reduced instruction set computer architecture
%R UCB/CSD 83/141
%S Computer Science Division
%X This is the Ph. D. thesis written by one of the designers of the RISC I & II.
There is a nice summary of the RISC project, the rationale behind
it, and implementation details of the RISC II chip.
%K risc reduced instruction set computer restricted architecture

%T Reduced Instruction Set Computer Architectures for VLSI
%l technical-report
%A Manolis G. H. Katevenis
%C Berkeley, California 94720
%D 1983
%I CSD/EECS U. C. Berkeley
%M October
%R Ph.D. Thesis, U.C. Berkeley, Tech. Report UCB/CSD 83/141
%X Received the 1984 ACM doctoral dissertation award. Published by
the MIT Press (1985). Reviewed in VLSI Design, Vol. 6, No. 8, August
%K risc reduced instruction set computer restricted architecture

%T An Analysis of the UCB-RISC in the Gallium Arsenide Environment
%l journal-article
%A K. Keirn
%A V. Milutinovic
%D 1985
%J ICCD 85
%M October
%P 396-399
%X Proof that they'll publish anything.
%K risc reduced instruction set computer restricted architecture

%T Are RISCs Subsets of CISCs?
%l journal-article
%A E. Korthaver
%A L. Richter
%D 1984
%J Microprocessing and Microprogramming
%M August
%K risc reduced instruction set computer restricted architecture

%T Hints for Computer System Design
%l journal-article
%A B. W. Lampson
%D 1983
%J ACM Operating Systems Review
%M October
%N 5
%P 33-48
%V 17
%K risc reduced instruction set computer restricted architecture

%T Pyramid builds UNIX Supermini with reduced-instruction-set architecture
%l journal-article
%A Geoff Lewis
%D 1983
%J Mini-Micro Systems
%M August
%P 17-20
%K risc reduced instruction set computer restricted architecture

%T HP Precision Architecture Performance Analysis
%l journal-article
%A Joseph A. Lukes
%D 1986
%J Hewlett-Packard Journal
%M August
%N 8
%P 30-39
%V 37
%K risc reduced instruction set computer restricted architecture

%T Empirical Evaluation of Some Features of Instruction Set
Processor Architectures
%l journal-article
%A A. Lunde
%D 1972
%J CACM
%M March
%K risc reduced instruction set computer restricted architecture

%T Instruction-Level Program and Processor Modeling
%l journal-article
%A M. MacDougall
%D 1984
%J Computer
%M July
%K risc reduced instruction set computer restricted architecture

%T A Risky New Architecture for the Future?
%l journal-article
%A Gregory MacNicol
%D 1985
%J Digital Design
%M March
%K risc reduced instruction set computer restricted architecture

%T The HP Precision Simulator
%l journal-article
%A Daniel J. Magenheimer
%D 1986
%J Hewlett-Packard Journal
%M August
%N 8
%P 40-43
%V 37
%K risc reduced instruction set computer restricted architecture

%T Hewlett-Packard Precision Architecture: The Processor
%l journal-article
%A Michael J. Mahon
%A Ruby Bei-Loh Lee
%A Terrence C. Miller
%A Jerome C. Huck
%A William R. Bryg
%D 1986
%J Hewlett-Packard Journal
%M August
%N 8
%P 4-21
%V 37
%K risc reduced instruction set computer restricted architecture

%T RISC Chips
%l journal-article
%A John Markoff
%D 1984
%J Byte
%K RISC
%M November
%N 11
%P 191-206
%V 9
%K risc reduced instruction set computer restricted architecture

%T Software Impact on Microcomputer Architecture
%l journal-article
%A Richard J. Markowitz
%D 1981
%J Compcon Spring 81
%M February
%P 40-48
%K risc reduced instruction set computer restricted architecture

%T Optimization of Range Checking
%l proceedings-article
%A Victoria Markstein
%A John Cocke
%A Peter Markstein
%D 1982
%J Proc. of the Sigplan 82 Symp. on Compiler Construction
%M June
%P 114-119
%X These proceedings appear as Sigplan Notices, vol. 17, no. 6.
An earlier version of this paper was issued as IBM Research
Report RC 8456(36801), September 1980.
%K risc reduced instruction set computer restricted architecture

%T What's All the Fuss About RISC?
%l journal-article
%A John R. Mashey
%D 1986
%J Unix Review
%M February
%N 2
%P 37-50
%V 4
%K risc reduced instruction set computer restricted architecture

%T IBM Mini a Radical Departure
%l journal-article
%A Vin McLellan
%D 1979
%J Datamation
%K RISC
%M October
%N 11
%P 53-55
%V 25
%K risc reduced instruction set computer restricted architecture

%T Simplicity is Focus in Efforts to Increase Computer Power
%l journal-article
%A M. Miller
%D 1985
%J Wall Street Journal
%M August
%K risc reduced instruction set computer restricted architecture

%T Gambling on RISC
%l journal-article
%A J. Moad
%D 1986
%J Datamation
%M June
%K risc reduced instruction set computer restricted architecture

%T New RISC Machines Appear as Hybrids with Both RISC and CISC
Features
%l journal-article
%A N. Mokhoff
%D 1986
%J Computer Design
%M April
%K risc reduced instruction set computer restricted architecture

%T New RISC machines appear as hybrids with both RISC and CISC features
%l journal-article
%A Nicolas Mokhoff
%D 1986
%J Computer Design
%M April 1
%N 7
%P 22-25
%V 25
%K risc reduced instruction set computer restricted architecture

%T A CMOS RISC Processor with Integrated Systems Functions
%l proceedings-article
%A J. Moussoris
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T A CMOS RISC Processor with Integrated System Functions
%l journal-article
%A J. Moussouris
%A L. Crudele
%A D. Freitas
%A C. Hansen
%A E. Hudson
%A R. March
%A S. Przybylski
%A T. Riordan
%A C. Rowen
%A D. Van't Hof
%D 1986
%J Compcon Spring 86
%M March
%P 126-131
%K risc reduced instruction set computer restricted architecture

%T C Compiler Implementation Issues on the Clipper
%l proceedings-article
%A D. Neff
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T Clipper Microprocessor Architecture Overview
%l proceedings-article
%A L. Neff
%D 1986
%J Proc. COMPCON Spring 1986
%M March
%K risc reduced instruction set computer restricted architecture

%T RISC Machines
%l journal-article
%A S. Ohr
%D 1985
%J Electronic Design
%M January
%K risc reduced instruction set computer restricted architecture

%T Tradeoffs In The Design of A System For High Level Language Interpretation
%l journal-article
%A Fernando C. Colon Osorio
%A Yale N. Patt
%D 1983
%J ICCD 83
%M October
%P 620-625
%K risc reduced instruction set computer restricted architecture

%T Assessing RISCs in High Level Language Support
%l journal-article
%A D. Patterson
%A R. Piepho
%D 1982
%J IEEE Micro
%M November
%K risc reduced instruction set computer restricted architecture

%T Architecture of a VLSI Instruction Cache for a RISC
%l proceedings-article
%A D. Patterson
%D 1983
%J Proc. 10th Computer Architecture Conference
%K risc reduced instruction set computer restricted architecture

%T Reduced Instruction Set Computers
%l journal-article
%A D. Patterson
%D 1985
%J CACM
%M January
%K risc reduced instruction set computer restricted architecture

%T RISC 1: A Reduced Instruction Set VLSI Computer
%l proceedings-article
%A D. A. Patterson
%A C. H. Sequin
%D 1981
%J 8th. Ann. Symp. on Computer Architecture
%K risc reduced instruction set computer restricted architecture
%M May
%P 443-457
%K risc reduced instruction set computer restricted architecture

%T A VLSI RISC
%l journal-article
%A D. A. Patterson
%A C. H. Sequin
%D 1982
%I IEEE
%J Computer
%K risc reduced instruction set computer architecture restricted
%M September
%N 9
%P 8-21
%V 15
%K risc reduced instruction set computer restricted architecture

%T A VLSI RISC
%l journal-article
%A D. A. Patterson
%A C. H. Sequin
%D 1982
%J Computer
%K risc reduced instruction set computer architecture restricted
%M September
%N 9
%P 8-21
%V 15
%K risc reduced instruction set computer restricted architecture

%T RISC II: A Sucessful Successor
%l journal-article
%A D. A. Patterson
%D 1983
%J VLSI Design
%M September
%K risc reduced instruction set computer restricted architecture

%T Design Considerations for Single-Chip Computers of the Future
%l journal-article
%A David A. Patterson
%A Carlo H. Sequin
%D 1980
%J IEEE Trans. Computers
%M February
%N 2
%P 108-116
%V C-29
%K risc reduced instruction set computer restricted architecture

%T The Case for the Reduced Instruction Set Computer
%l journal-article
%A David A. Patterson
%A David R. Ditzel
%D 1980
%J Computer Architecture News
%M October
%N 6
%P 25-33
%V 8
%K risc reduced instruction set computer restricted architecture

%T A RISCy APPROACH TO COMPUTER DESIGN
%l proceedings-article
%A David A. Patterson
%D 1982
%I IEEE Computer Society press
%J Digest of papers, Spring COMPCON 82
%K risc reduced instruction set computer architecture restricted
%M Spring
%P 8-14
%K risc reduced instruction set computer restricted architecture

%T A RISCy Approach to Computer Design
%l journal-article
%A David A. Patterson
%D 1982
%J Compcon Spring 82
%M February
%P 8-14
%K risc reduced instruction set computer restricted architecture

%T Assessing RISCs in High-Level Language Support
%l journal-article
%A David A. Patterson
%A Richard S. Piepho
%D 1982
%J IEEE Micro
%M November
%N 4
%P 9-19
%V 2
%X An earlier version of this article, entitled 'RISC Assesment: A High-Level
Language Experiment' was presented at the Ninth Annual Symposium on Computer
Architecture, April 1982.
%K risc reduced instruction set computer restricted architecture

%T A VLSI RISC
%l journal-article
%A David A. Patterson
%A Carlo H. Sequin
%D 1982
%J Computer
%M September
%N 9
%P 8-21
%V 15
%X An earlier version of this article, entitled 'RISC I: A Reduced Instruction
Set VLSI Computer' appeared in the Proc. Eighth Int'l Symp. on Computer
Architecture, pp. 443-457, May 1981.
%K risc reduced instruction set computer restricted architecture

%T Architecture of a VLSI Instruction Cache
%l journal-article
%A David A. Patterson
%A Phil Garrison
%A Mark Hill
%A Dimitris Lioupis
%A Chris Nyberg
%A Tim Sippel
%A Korbin Van\0Dyke
%D 1983
%J 10th Annual Symp. Computer Architecture
%M June
%P 108-116
%K risc reduced instruction set computer restricted architecture

%T Microprogramming
%l journal-article
%A David A. Patterson
%D 1983
%J Scientific American
%M March
%N 3
%P 50-57
%V 248
%K risc reduced instruction set computer restricted architecture

%T VLSI Systems Building: A Berkeley Perspective
%l journal-article
%A David A. Patterson
%D 1984
%J 1984 Conference on Advanced Research in VLSI, M.I.T.
%M January
%P 84-91
%K risc reduced instruction set computer restricted architecture

%T RISC Watch
%l journal-article
%A David A. Patterson
%D 1984
%J Computer Architecture News
%M March
%N 1
%P 11-19
%V 12
%K risc reduced instruction set computer restricted architecture

%T Reduced Instruction Set Computers
%l journal-article
%A David A. Patterson
%D 1985
%J Communications of the ACM
%M January
%N 1
%P 8-21
%V 28
%K risc reduced instruction set computer restricted architecture

%T The VLSI Circuitry of RISC I
%l technical-report
%A J. B. Peek
%D 1983
%I U. C. Berkeley
%M June
%R Computer Science Technical Report UCB/CSD 83/1135
%K risc reduced instruction set computer restricted architecture

%T A 32b Microporcessor for Smalltalk
%l journal-article
%A Joan M. Pendelton
%A Shing I. Kong
%A E. Will Brown
%A Frank Dunlap
%A Christopher Marino
%A David M. Ungar
%A David A. Patterson
%A David A. Hodges
%D 1986
%J ISSCC 86
%M February
%P 32-33,293
%K risc reduced instruction set computer restricted architecture

%T ...but will RISC run LISP (a feasiblity study)
%l technical-report
%A C. Ponder
%D 1983
%I U. C. Berkeley
%M August
%R Computer Science Technical Report UCB/CSD 83/122
%K risc reduced instruction set computer restricted architecture

%T The Acorn RISC Machine
%l journal-article
%A Dick Pountain
%D 1986
%J Byte
%M January
%N 1
%P 387-393
%V 11
%K risc reduced instruction set computer restricted architecture

%T Organization and VLSI Implementation of MIPS
%l journal-article
%A S. Przybylski
%A T. Gross
%A J. Hennessy
%A N. Jouppi
%A C. Rowen
%D 1984
%J Journal of VLSI Design and Computer Systems
%M Spring
%X Stanford University Computer Systems Laboratory Technical Report No. 84-259
%K risc reduced instruction set computer restricted architecture

%T The Design Verification and Testing of MIPS
%l journal-article
%A Steven Przybylski
%D 1984
%J 1984 Conference on Advanced Research in VLSI, M.I.T.
%M January
%P 100-109
%K risc reduced instruction set computer restricted architecture

%T The 801 Minicomputer
%l proceedings-article
%A G. Radin
%D 1982
%J Proceedings from the Symposium on Architectural Support for
Programming Languages and Operating Systems
%M March
%P 39-47
%K risc reduced instruction set computer restricted architecture

%T The 801 Minicomputer
%l proceedings-article
%A George Radin
%D 1982
%J Proc. Symp. Architectural Support of Programming Languages and Operating Systems
%M March
%P 39-47
%X This conference proceedings was also issued as Sigplan Notices,
vol. 14, no. 4, April 1982 and Computer Architecture News, vol. 10,
no. 2, March 1982.
%K risc reduced instruction set computer restricted architecture

%T The 801 Minicomputer
%l journal-article
%A George Radin
%D 1983
%J IBM J. Res. Dev.
%M May
%N 3
%P 237-246
%V 27
%K risc reduced instruction set computer restricted architecture

%T Applying RISC Theory to a Large Computer
%l journal-article
%A R. Ragan-Kelly
%A R. Clark
%D 1983
%J Computer Design
%K mips risc reduced restricted instruction set computer architecture
pipelining microcoding
%M November
%N 13
%P 191-198
%V 22
%X Description of the Pyramid 90x by people at Pyramid.
%K risc reduced instruction set computer restricted architecture

%T A pipelined 32 bit NMOS microprocessor
%l proceedings-article
%A C. Rowen
%A S. A. Przybylski
%A N. P. Jouppi
%A T. R. Gross
%A J. D. Shott
%A J. Hennessy
%D 1984
%J Proc. IEEE Int. Solid-State Circuits Conference
%M February
%P 180-181
%K risc reduced instruction set computer restricted architecture

%T RISC VLSI Design for System-Level Performance
%l journal-article
%A Chris Rowen
%A Les Crudele
%A Dan Freitas
%A Craig Hansen
%A Ed Hudson
%A John Kinsel
%A John Moussouris
%A Steven Przybylski
%A Tom Riodan
%D 1986
%J VLSI Systems Design
%M March
%N 3
%P 81-88
%V 7
%K risc reduced instruction set computer restricted architecture

%T OPA - A New Architecture for Pascal-Like Languages
%l journal-article
%A P. Schulthess
%A F. Vonaesch
%D 1982
%I ACM
%J ACM Computer Architecture News
%K stack RISC language directed
%M December
%N 6
%P 9
%V 10
%K risc reduced instruction set computer restricted architecture

%T Pyramid Challenges DEC with RISC Supermini
%l journal-article
%A M. Seither
%D 1985
%J Mini-Micro Systems
%M August
%K risc reduced instruction set computer restricted architecture

%T Design and Implementation of RISC I
%l book
%A C. H. Sequin
%A D. A. Patterson
%B VLSI Architecture
%C Englewood Cliffs, New Jersey
%D 1982
%E B. Randell and P. C. Treleaven
%I Prentice Hall
%X This book is a collection lecture notes given at the 1982 Advanced
Course on VLSI Architecture, held at the University of Bristol, England.
%K risc reduced instruction set computer restricted architecture

%T MIPS, Dhrystones, and Other Tales
%l journal-article
%A O. Serlin
%D 1986
%J Datamation
%M June
%K risc reduced instruction set computer restricted architecture

%T Datapath Design for RISC
%l proceedings-article
%A R. W. Sherburne
%A M. G. H. Katevenis
%A D. A. Patterson
%A C. H. Sequin
%C Cambridge, MA
%D 1982
%I MIT
%J Proc. Conf. on Adv. Research in VLSI
%M January
%P 53-62
%K risc reduced instruction set computer restricted architecture

%T Processor design tradeoffs in VLSI
%l technical-report
%A R. W. Sherburne
%D 1984
%I CSD/EECS U. C. Berkeley
%M April
%R Ph.D. Dissertation
%K risc reduced instruction set computer restricted architecture

%T A 32-bit Microprocessor with a large register file
%l journal-article
%A R. W. Sherburne
%A M. G. H. Katevenis
%A D. A. Patterson
%A C. H. Sequin
%D 1984
%J 31st International Solid States Circuit Conference
%M February
%X Also appears in the IEEE Journal of Solid-State Circuits, vol. SC-19,
no. 5, October 1984.
%K risc reduced instruction set computer restricted architecture

%T Local Memory in RISCs
%l journal-article
%A Robert W. Sherburne\0Jr.
%A Manolis G.H. Katevenis
%A David A. Patterson
%A Carlo H. Sequin
%D 1983
%J ICCD 83
%M October
%P 149-152
%K risc reduced instruction set computer restricted architecture

%T A Study of Instruction Set Cache Organization and Replacement Policies
%l proceedings-article
%A J. E. Smith
%A J. R. Goodman
%D 1983
%J Proc. 10th Annual ACM Symp. Computer Architecture
%M June
%P 132-136
%K risc reduced instruction set computer restricted architecture

%T Acorn Goes to Market with RISC Microprocessor
%l journal-article
%A Kevin Smith
%D 1985
%J Electronics
%M August 5
%N 31
%P 14-15
%V 58
%X Describes the ARM (Acorn RISC Machine) chip.
%K risc reduced instruction set computer restricted architecture

%T Industry Insider: Why the RISC route?
%l journal-article
%A Mark G. Sobell
%D 1985
%J Unix Review
%M August
%N 8
%P 70-74
%V 3
%K risc reduced instruction set computer restricted architecture

%T Simulation and Performance Evaluation of the RISC Architecture
%l technical-report
%A Y. Tamir
%D 1981
%M March
%R ERL Memo M81/17, U.C. Berkeley
%K risc reduced instruction set computer restricted architecture

%T Stratagies for Managing the Register File in RISC
%l journal-article
%A Y. Tamir
%A C. H. Sequin
%D 1983
%J IEEE Trans. Comp.
%M November
%N 11
%V C-32
%K risc reduced instruction set computer restricted architecture

%T Implications of Structured Programming for Machine Architecture
%l journal-article
%A A. Tanenbaum
%D 1978
%J CACM
%M March
%K risc reduced instruction set computer restricted architecture

%T VLSI Processor Architectures
%l journal-article
%A Phillip C. Treleaven
%D 1982
%J Computer
%M June
%N 6
%P 33-45
%V 15
%K risc reduced instruction set computer restricted architecture

%T Arcitecture of SOAR: Smalltalk on a RISC
%l proceedings-article
%A David Ungar
%A Ricki Blau
%A Peter Foley
%A Dain Samples
%A David Patterson
%D 1984
%J Proceedings of the 11th Symposium on Computer Architecture
%M June
%P 188-197
%K risc reduced instruction set computer restricted architecture

%T Toward Simpler, Faster Computers
%l journal-article
%A P. Wallich
%D 1985
%J IEEE Spectrum
%M August
%K risc reduced instruction set computer restricted architecture

%T Towards simpler, faster computers
%l journal-article
%A Paul Wallich
%D 1985
%J IEEE Spectrum
%M August
%N 8
%P 38-45
%V 22
%K risc reduced instruction set computer restricted architecture

%T IBM RT Personal Computer Technology
%l technical-report
%A F. Waters, ed.
%D 1986
%I IBM
%R SA23-1057
%K risc reduced instruction set computer restricted architecture

%T A Language-Oriented Approach for Implementing Branches: Structured Control Flow
%l journal-article
%A Robert G. Wedig
%D 1984
%J Int'l Workshop on High-Level Computer Architecture
%M May
%K risc reduced instruction set computer restricted architecture

%T A Case Study of VAX-11 Instruction Set Usage For Compiler Execution
%l proceedings-article
%A Cheryl A. Wiecek
%D 1982
%J Proc. Symp. Architectural Support of Programming Languages and Operating Systems
%M March
%P 177-184
%X This conference proceedings was also issued as Sigplan Notices,
vol. 14, no. 4, April 1982 and Computer Architecture News, vol. 10,
no. 2, March 1982.
%K risc reduced instruction set computer restricted architecture

%T Keeping Jump Instructions out of the Pipeline of a RISC-Like Computer
%l journal-article
%A M. V. Wilkes
%D 1983
%I ACM
%J Computer Architecture News
%M Dec
%N 5
%P 5-7
%V 11
%K risc reduced instruction set computer restricted architecture

%T Keeping Jump Instructions out to the pipeline of a RISC-like Computer
%l journal-article
%A M. V. Wilkes
%D 1983
%J Computer Architecture News
%M December
%N 5
%P 5-7
%V 11
%K risc reduced instruction set computer restricted architecture

%T Keynote Address: The Processor Instruction Set
%l proceedings-article
%A Maurice G. Wilkes
%D 1982
%J MICRO 15, Proc. 15th Annual Workshop on Microprogramming
%M October
%P 3-5
%K risc reduced instruction set computer restricted architecture

%T Compilers and Computer Architecture
%l journal-article
%A W. A. Wulf
%D 1981
%J Computer
%M July
%N 7
%P 41-48
%V 14
%K risc reduced instruction set computer restricted architecture

%K risc reduced instruction set computer restricted architecture
SHAR_EOF
fi
exit 0
# End of shell archive
--
Patrick Powell, Dept. Computer Science, 136 Lind Hall, 207 Church St. SE,
University of Minnesota, Minneapolis, MN 55455 (612)625-3543/625-4002