[comp.arch] TMS320C30

wsmith@m.cs.uiuc.edu (11/19/88)

Has anyone thought of building a PC with the TMS320C30 (not to be confused with
the NS32032)?   It is rated at 33 MFLOPS and 16 MIPS (your milage may vary).

The architecture from what I've read so far works by throwing lots of busses 
at the data flow paths and have a bunch of dual ported memory on chip.

Besides the fact that the TMS320C30 is a signal processing computer, are there
reasons this chip hasn't been used?

Bill Smith
wsmith@cs.uiuc.edu
uiucdcs!wsmith

brucek@hpnmdla.HP.COM (Bruce Kleinman) (11/22/88)

+-------
| Besides the fact that the TMS320C30 is a signal processing computer, are
| there reasons this chip hasn't been used?
+-------
Availability is curently on a "one sample per customer" basis at $1300 a pop.

Early lifecycle aside, this a sharp chip.  It seems to be "aimed" at the
embedded marketplace, having things like...
	* an on-chip DMA unit
	* a pair of UARTs
	* on chip maskable ROM

Not that one couldn't use these on a general purpose machine; they are just
usually found on microcontrollers.  In addition to the above, a few other
noteworthy features for GP use...
	* on-chip RAM of useful size
	* on-chip FPU with excellent performance 
	* lots of on-chip buses for flexibility
	* a pair of off chip buses (a memory bus and an "I/O" bus)