rick@cs.arizona.edu (Rick Schlichting) (01/10/91)
Call for Attendance
International Symposium on
Shared Memory Multiprocessing (ISSMM)
Sponsored by Information Processing Society of Japan
With the Support from
International Information Science Fundation
IBM Japan
NEC
Conference Chair Takashi Masuda (University of Tokyo)
Treasurer Kazuya Tago (IBM Japan)
Local Arrangement Chair Yoshikatsu Tada (Electro-Comm. University)
Program Chair Norihisa Suzuki (IBM Japan)
Program Committee Tilak Agerwala (IBM)
Forest Baskett (Silicon Graphics)
Ed Clarke (CMU)
David Gifford (MIT)
Jim Goodman (University of Wisconsin)
John Hennesy (Stanford University)
Paul Hilfinger (U. C. Berkeley)
Nobuhiko Koike (NEC)
Chuck Thacker (DEC)
Shinji Tomita (Kyushu University)
Akinori Yonezawa (University of Tokyo)
For more information contact
Dr. Norihisa Suzuki
IBM Tokyo Research Lab.
5-19 sanbancho, Chiyoda-ku, Tokyo, 102 JAPAN
Phone: 81-3-3288-8300
FAX: 81-3-3265-4251
E-mail: NSUZUKI@JPNTSCVM.BITNET
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Registration Form
~~~~~~~~~~~~~~~~~
Fee
~~~
30,000 Yen
Registration fee includes: Monday Reception, Wednesday Banquet, Coffee
~~~~~~~~~~~~~~~~~~~~~~~~~~ breaks, and a copy of proceedings.
Note: the hotel registration includes breakfast.
Additional banquet ticket at 10,000 Yen
Name: __________________________________________________________________
Affiliation: ___________________________________________________________
Address: _______________________________________________________________
________________________________________________________________________
Fax: _______________________________
E-mail: ____________________________
Payment Form (Please check appropriate box)
Check in Yen ( )
Credit Card ( )
Visa ( ) Number: _____________________
M/C ( ) Expiration Date: ____________
A/E ( )
Please fill out the above registration form and mail or fax it to:
Dr. Kazuya Tago
IBM Tokyo Research Laboratory
5-19 Sanbancho
Chiyoda-ku, Tokyo 102 JAPAN
FAX: 81-3-3265-4251
PHONE: 81-3-3288-8406
E-MAIL: TAGO@TRLVM1.IINUS1.IBM.COM
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Hotel Registration
~~~~~~~~~~~~~~~~~~
Conference Hotel
~~~~~~~~~~~~~~~~
Sunshine Prince Hotel
1-5, Higashi-Ikebukuro 3-chome, Toshima-ku, Tokyo 170
Phone: 81-3-3988-1111
Fax: 81-3-3983-0126
Contact Person: Mr. Hideki Matsunaga
Rate
~~~~
Single Y13,000
Large Single Y17,000
Deluxe Twin Y23,000
The rate includes breakfast and service charge.
Transportation
~~~~~~~~~~~~~~
There is a limousine from Narita airport (Y2,700)
to the hotel directly, that leaves every half an hour.
Reservation
~~~~~~~~~~~
Please contact directly.
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PROGRAM
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Monday, April 1 1991
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19:00-21:00 Reception
~~~~~~~~~~~~~~~~~~~~~
Tuesday, April 2 1991
~~~~~~~~~~~~~~~~~~~~~
9:00 Opening Remarks N. Suzuki (IBM Tokyo Research Lab.)
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Session 1 Experience I Chair: T. Masuda (U. Tokyo)
~~~~~~~~~~~~~~~~~~~~~~~
9:15 Experiences with Parallel Symbolic Computation Algorithms
E. M. Clarke, D. E. Long, S. Michaylov, S. A. Schwab, J. P. Vidal (CMU),
and S. Kimura (Kobe University)
9:45 Experimental Evaluation of Algorithmic Performance on Two shared Memory
Multiprocessors
A. Sivasubramaniam, G, Shah, J. Lee, U. Ramachandran, and
H. Venkateswaran (Georgia Institute of Technology)
10:15 Cofffee Break
~~~~~~~~~~~~~
Session 2 Compiler Chair: T. Agerwala (IBM)
~~~~~~~~~~~~~~~~~~~
10:45 An Empirical Investigation of the Effectiveness and Limitations of
Automatic Parallelization
J. P. Singh and J. L. Hennesy (Stanford University)
11:15 Fine-Grain Loop Scheduling for MIMD Machines
C. J. Brownhill, K-C. Kim, and A. Nicolau (UC Irvine)
11:45 Lunch Break
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Session 3 Scalable Architecture I Chair: F. Baskett (Silicon Graphics)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1:15 A Scalable Cache Coherence Mechanism for Large Scale Multiprocessors
S. L. Scott (U. Wisconsin)
1:45 Fault-Tolerant Design for Multistage Routing Networks
A. DeHon, T. Knight, and H. Minsky (MIT)
2:15 Dynamic Pointer Allocation for Scalable Cache Coherence Directories
R. Simoni and M. Horowitz(Stanford University)
2:45 Coffee Break
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Session 4 Scalable Architecture II Chair: J. R. Goosman (U. Wisconsin)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3:15 Cenju: A Multiprocessor System with a Distributed Shared Memory Scheme
for Modular Circuit Simulation
T. Nakata, N. Tanabe, N. Kajihara, S. Matsushita, H. Onozuka, and
Y. Asano, and N. Koike (NEC)
3:45 Latency Tolerance in Large-Scale Multiprocessors
K. kurihara, D. Chaiken, and A. Agerwala (MIT)
4:15 Overview of the Stanford DASH Multiprocessor
D. Lenoski, J. Laudon, K. Gharachorloo,W-D. Weber, A. Gupta, and
J. Hennesy (Stanford University)
Wednesday, April 3 1991
~~~~~~~~~~~~~~~~~~~~~~~
Session 5 Tools Chair: N. Koike (NEC)
~~~~~~~~~~~~~~~~
9:00 Restructuring a Parallel Simulation to Improve Cache Behavior in a
Shared-Memory Multiprocessor: A First Experience
D. R. Cheriton, H. A. Goosen, and P. Machanick (Stanford University)
9:30 A Replay Mechanism for Mostly Functional Paarallel Programs
R.H. Halstead, Jr. (DEC Cambridge Research Lab.) and D. A. Kranz (MIT)
10:00 Coffee Break
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Session 6 Operating System Chair: D. Gifford (MIT)
~~~~~~~~~~~~~~~~~~~~~~~~~~~
10:30 MUSTARD: A Mutiprocessor UNIX for Embedded Real-Time Systems
S. Hiroya, T. Momoi, and K. Nihei (NEC)
11:00 Abstracting Data-Representation and Partitioning-Scheduling
G. A. Alverson and D. Notkin (U. Washington)
11:30 An Analysis of QLOB Synchronization and prefetching in Shared-Memory
Multiprocessors
P. J. Woest and J. R. Goodman (U. Wisconsin)
12:00 Lunch Break
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Session 7 Evaluation and Superscalar Chair: P. Hilfinger (UC Berkeley)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1:30 Throughput and Fairness Analysis of Prioritized Multiprocessor
Arbitration Protocol
M. Ishigaki (Nomura Research Institute), H. Takagi (IBM Tokyo Research
Lab.), Y. Takahashi, and T. Hasegawa (U. Kyoto)
2:00 Fine Grain Software Pipelining of Non-Vectorizable Nested Loops
K-C. Kim and A. Nicolau (UC Irvine)
2:30 A Dynamic Instruction Delivery Pipeline for Superscalar Architecture
T. Chiueh and S-I. Doong (UC Berkeley)
3:00 Lunch Break
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Session 8
~~~~~~~ ~
3:00 Panel Discussion
6:00 Banquet Tenzan Room at Sunshine Prince Hotel
~~~~~~~~~~~~~
Session 9 Experience II Chair: E. M. Clarke (CMU)
~~~~~~~~~~~~~~~~~~~~~~~~~
9:00 Experience with the Firefly Multiprocessor Workstation
S. Owicki (DEC Systems Research Center)
9:30 Design and Evaluation of Snoop-Cache-Based Multiprocessor, TOP-1
S. Shimizu, N. Ohba, A. Moriwaki, and T. Nakada (IBM Tokyo Research
Lab.)
10:00 Coffee Break
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Session 10 Cache Chair: J. L. Hennesy (Stanford University)
~~~~~~~~~~~~~~~~~
10:30 The Kyushu University Reconfigurable Parallel Processor -Cache
Architecture and Cache Coherence Schemes-
S. Mori, K. Murakami, E. Iwata, A. Fukuda, and S. Tomita
(Kyushu University)
11:00 An Evaluation of Cache Coherence Protocols for MIN-Based Multiprocessors
S. J. Baylor, K. P. McAuliffe, and B. D. Rathi (IBM TJ Watson Research
Center)
11:30 Formal Verification of the Gigamax Cache Consistency Protocol
K. L. McMillan (CMU) and J. Schwalbe (Encore Computer Co.)