jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) (10/03/89)
I was recently reading a description of the Stanford MIPS RISC
processor (1982/3 vintage). The desciption notes that this
processor had a 5-stage pipeline but had NO pipeline interlock
logic. Instead, all potential code for the processor had to be
pre-processed by a program called a "reorganizer" which examined
the code and removed all pipeline dependencies, either by code
reorganization or by insertion of NOPs.
The rationale behind the decision to eliminate pipeline interlock
logic was, as you might guess, speed and (die) space.
So...my question: most (all?) of the current RISC processors
(29000, 88000, 80860, etc) include pipeline interlock logic.
Could someone familiar with these processors comment on the
implications of this decision:
-- How much of the total chip area is occupied by
pipeline interlock logic?
-- If the interlock logic were eliminated, could the
processor cycle time be decreased? By how much?
-- How long (in person-weeks/years, whatever) did it take
to design the interlock logic? How long did it take to
design the entire chip?
** Jeff Kuskin, Dartmouth College
** E-Mail: jskuskin@eleazar.dartmouth.edukhb%chiba@Sun.COM (chiba) (10/03/89)
In article <15904@dartvax.Dartmouth.EDU> jskuskin@eleazar.dartmouth.edu (Jeffrey Kuskin) writes: > >So...my question: most (all?) of the current RISC processors >(29000, 88000, 80860, etc) include pipeline interlock logic. MIPSco and SPARC also At Hot Chips, John M. mentioned interlocks as one of the nice features of the MIPSco chips. >Could someone familiar with these processors comment on the >implications of this decision: > > -- How much of the total chip area is occupied by > pipeline interlock logic? Not much. > > -- If the interlock logic were eliminated, could the > processor cycle time be decreased? By how much? In general, very little if at all. My drinking buddies who are hw jocks think they know how to do such things in parallel with real work. :> > > -- How long (in person-weeks/years, whatever) did it take > to design the interlock logic? Dunno. Certainly seems unlikely to anywhere near as costly as the software havoc not having interlocks costs. Aside from the compiler development, inevitable bugs introduced by hand coders and the like, is the fact that your binaries simply won't run on the next generation device (unless you really constrain the hw jocks). Upgrading your machine --> all new software is unpopular. Sufficiently so that it seems that few if any commerical designs will completely skip interlocks. > > > > ** Jeff Kuskin, Dartmouth College > > ** E-Mail: jskuskin@eleazar.dartmouth.edu Keith H. Bierman |*My thoughts are my own. !! kbierman@sun.com It's Not My Fault | MTS --Only my work belongs to Sun* I Voted for Bill & | Advanced Languages/Floating Point Group Opus | "When the going gets Weird .. the Weird turn PRO"