mark@mips.COM (Mark G. Johnson) (03/21/90)
Many of the articles referenced above discuss the idea of using
dRAM cells for building on-chip cache RAMs. The hope is that
this will achieve more bits of RAM in a given amount of die area
than static 6T or 4T,2R sRAM cells.
I'd like to put in a plug for a technical paper that will appear soon:
"Non-Refreshing Dynamic RAM for On-Chip Cache Memories",
D.D. Lee and R.H. Katz, Xerox & UC Berkeley, to be presented
June 9, 1990 at the Symposium on VLSI Circuits in Honolulu, HI.
Their approach looks interesting and workable. It *doesn't* require
that one specific node should leak as fast or faster than another
(set of) dynamic nodes. Go to the conference, enjoy Hawaii, see
the paper presented, make up your own mind.
--
-- Mark Johnson
MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
(408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}