colwell@mfci.UUCP (Robert Colwell) (12/22/88)
In article <2523@ficc.uu.net> karl@ficc.uu.net (karl lehenbauer #) writes: >In article <8841@sequent.UUCP>, rgb@sequent.UUCP (Bob Bond) writes: >> I have heard "Parity is for farmers" attributed to Cray. >> Does anyone know if this is accurate? > >I know the CDC 6600, Cyber 70 and 170 series machines did not have parity. >From what I heard Seymour felt that parity didn't buy much -- detection >of a parity error meant death for the running program at the least and >maybe even for the OS. There was always the chance that the parity error >would occur in the parity bit, causing a parity error when there was >no actual data error. Almost all the commercial machines I know about use SEC/DED ECC on their memories but parity checking on the buses. Are there really machines that use ECC on their buses? Why? >The Cray line has error correction/double error detection, an innovation >(not pioneered by them) that buys a good deal more than parity detection >alone, hence it's in there. Only on memories, or in systems that are designed for high reliability. I think of parity detection as being the last resort. I think you could make a case that if the user microprograms a machine (writing her own assembly for a RISC w/o hw interlocks, for instance), and oversubscribes a resource, then the hardware doesn't necessarily owe her detection of that oversubscription. But if a transient causes a bit flip on a bus I think the user has the right to expect to be told that the program encountered something unexpected, so that she doesn't trust the answers. That's what parity is good for. Funny thing, though; seems like parity design and testing always gets put off until last in a design, and it is often the tightest path on the buses, so becomes a major hassle early in the debug phase. (Generic comment, not meant to apply to present employer!) Bob Colwell ..!uunet!mfci!colwell Multiflow Computer or colwell@multiflow.com 175 N. Main St. Branford, CT 06405 203-488-6090
baum@Apple.COM (Allen J. Baum) (12/23/88)
[] >In article <582@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes: > >Almost all the commercial machines I know about use SEC/DED ECC on >their memories but parity checking on the buses. Are there really >machines that use ECC on their buses? Why? There are machines that have an ECC code on the command lines- like a two out of 5 code. I think the VAXBI might do that. In general, I think that most designers believe that parity is adequate on anything that can be retried, like a bus transfer, but ECC is necessary for things that can't, like storage. Even then, static storage inside a CPU (registers, etc.) is usually only parity corrected, while dynamic storage (DRAMS), which are much more susceptible to failures, are ECC protected. -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum