gerry@zds-ux.UUCP (Gerry Gleason) (11/11/89)
In article <280003@hpdml93.HP.COM> sritacco@hpdml93.HP.COM (Steve Ritacco) writes: >> Anybody have information about the new 55 MIPS machine that MIPS Co. >> announced? For example, what technology is the processor, ECL? What are the >> specs for the cache design? What is the memory and I/O bandwidth? >It is an ECL implementation fabb'ed by BIT, as I understand it. >More info would be appreciated, especially any architectural >enhancements or changes over the R3000. Are you both talking about the same chip? The BIT processor that I know about is a SPARC processor. There was an article in High Performance Systems about it. I believe they quoted an 80MHz clock rate and 60 MIPS performance, and also claimed that at least some of the early chips would run at 100MHz. Gerry Gleason
rogerk@mips.COM (Roger B.A. Klorese) (11/11/89)
In article <12@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes: >In article <280003@hpdml93.HP.COM> sritacco@hpdml93.HP.COM (Steve Ritacco) writes: >>It is an ECL implementation fabb'ed by BIT, as I understand it. >>More info would be appreciated, especially any architectural >>enhancements or changes over the R3000. >Are you both talking about the same chip? The BIT processor that I >know about is a SPARC processor. There was an article in High Performance >Systems about it. I believe they quoted an 80MHz clock rate and 60 MIPS >performance, and also claimed that at least some of the early chips would >run at 100MHz. No, BIT has also fabbed for MIPS the R6000 chipset. [You're confused about this one because we didn't preannounce it by quite so long. ;-) Plus, it's not announced as a BIT product, but as a MIPS system component.] We are getting 55 MIPS (on our benchmark suite which shows the SPARCstation 3xx series as 16 MIPS, for comparison) at 67MHz; this may improve some by FCS early in 1990. -- ROGER B.A. KLORESE MIPS Computer Systems, Inc. phone: +1 408 720-2939 928 E. Arques Ave. Sunnyvale, CA 94086 rogerk@mips.COM {ames,decwrl,pyramid}!mips!rogerk "I want to live where it's always Saturday." -- Guadalcanal Diary
mslater@cup.portal.com (Michael Z Slater) (11/12/89)
>> Anybody have information about the new 55 MIPS machine that MIPS Co. >> announced? For example, what technology is the processor, ECL? What are th e >> specs for the cache design? What is the memory and I/O bandwidth? >> >> Chris Perleberg > >It is an ECL implementation fabb'ed by BIT, as I understand it. >More info would be appreciated, especially any architectural >enhancements or changes over the R3000. The new machine uses the R6000 CPU, which is currently being made by BIT. BIT is also making the R6010, a floating-point controller, and the R6020, a system bus interface chip. The FPC includes the adder/subtracter and registers, but the mul/div is in a standard BIT chip, which also has square root. The MIPS cpu implementation also uses a bunch of ECL gate arrays from Sony. MIPS is making the BIT and Sony chips available on a limited basis. Sometime next year, they will become available from NEC and Sony. MIPS is not releasing full details of the architectural extensions yet. There are new instructions to support some new capabilities of the FP hardware, some multiprocessor instructions, and some support for dynamically changing "endian-ness". Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677 sample issue sent on request