henry@zoo.toronto.edu (Henry Spencer) (09/21/90)
In article <11275@ganymede.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes: > Would a micro loose performance if it *NEVER* did > byte writes ? It would certainly be an advantage to > be able to turn them off for applications where > EDC was used---the CPU would do the RMW cycles... Typically the CPU won't be able to do an RMW as quickly as the memory, I would think, because the data paths are longer. The memory doesn't have to pass everything out over a bus and through the CPU and back. Also, if the memory is doing the work, the CPU can entrust the data to a write buffer and go do something else. It sounds like a useful approach for a low-cost system with EDC. That's kind of an odd animal, though, and I'm not sure it's in the interesting part of the design space. Maybe for ultra-high-reliability embedded applications? How much performance you lose from being unable to do byte writes depends on your applications. Many won't care much, some will lose badly. John might have some more specific comments. I note that the AMD 29000 started out with a no-partial-accesses memory interface, but changed it in the end... -- TCP/IP: handling tomorrow's loads today| Henry Spencer at U of Toronto Zoology OSI: handling yesterday's loads someday| henry@zoo.toronto.edu utzoo!henry