earl@mips.COM (Earl Killian) (05/24/88)
(See previous posting for background.) "n.a." = not applicable "???" = don't know > Architecture Reference Where is the architecture fully described? MIPS RISC Architecture by Gerry Kane Prentice Hall (available in book stores) > Peak native MIPS What is the clock cycle time? 25MHz What is the peak native MIPS rate? 25mips > Implementation technology What are the parameters of the implementation technology? 1.2micron CMOS How many chips of what kinds to build a typical cpu subsystem? How many pins on those chips? 1 R3000 cpu (172 pins) 1 R3010 fpu (84 pins) 4 R3020 write buffers (??? pins) 16 8Kx8 or 30 16Kx4 20ns SRAMs 4 FCTA 373 address latches 4 FCTA 374 read buffers > Instruction format What instruction sizes are used? 32 bits What size are immediate operands? 16 bits What size are branch displacements? 16 bits > Integer Registers How are the registers organized [simple, windowed]? simple How many total integer registers? 32 32-bit registers Hardwired zero register? yes, r0 > Integer Alu What is the logical latency/issue/repeat? 1/1/1 What is the shift latency/issue/repeat? 1/1/1 What is the add latency/issue/repeat? 1/1/1 What is the compare latency/issue/repeat? 1/1/1 How is 64 bit (signed/unsigned) integer addition supported and how many cycles? unsigned comparison for carry computation, 4 cycles total > Branches Which operand comparisons are implemented in the conditional branch instruction, and which require a separate instruction? branch instructions: A = B, A < 0, A <= 0, A > 0, A >= 0 separate comparison: A < B, A <= B, A > B, A >= B Where is the result of separate comparisons stored [registers, condition codes]? registers Which forms of branch delay are present in instruction set [execute N if no branch, execute N if branch, execute N always]? execute 1 always What are the taken and not-taken cycle counts for each branch type? 1 taken, 1 untaken > Loads/Stores What addressing mode(s) do load instructions use? register + 16-bit signed displacement What addressing mode(s) do store instructions use? register + 16-bit signed displacement Which load/store sizes are supported [8, 16, 32, 64]? 8, 16, 32 What is the load latency/issue/repeat? 2/1/1 What is the store latency/issue/repeat? 1/1/1 > Integer Multiply/Divide How is multiply is implemented [software, multiply step, hardware]? hardware How many cycles to perform 32x32->32 multiply? 13 How is divide is implemented [software, divide step, hardware]? hardware How many cycles to perform 32x32->32 divide? 36 How is 32x32->64 bit integer multiplication supported and how many cycles? hardware, 14 cycles How is 64/32->32,32 bit integer division supported and how many cycles? software, no cycle estimate > Floating Point Are floating point registers separate from integer registers? yes How many 32-bit floating point registers? 16 How many 64-bit floating point registers? 16 How many 80-bit floating point registers? n.a. How is floating point is implemented [software, coprocessor, on-chip]? What are the floating point operation latency/issue/repeats? 32-bit 64-bit 80-bit add 2/ 1/ 2 2/ 1/ 2 n.a. mul 4/ 1/ 4 5/ 1/ 5 n.a. div 12/ 1/12 19/ 1/19 n.a. sqrt n.a. n.a. n.a. Which floating point units can operate in parallel? add, mul, div Can floating point operate in parallel with integer? yes Are floating point exceptions precise? yes > Memory management Page size in bytes? 4096 How many bits in a virtual address? 32 What is the size of the user-mode address space? 2G How many bits in a physical address? 32 How many bits of address space id are added to virtual addresses, if any? 6 Translation cache [none, off-chip, on-chip]? on-chip Translation cache size in entries? 64 Translation cache associativity [direct-mapped, 2-set, 4-set, full]? full Translation cache miss handled by [software, hardware]? software > Caches Instruction cache [none, off-chip, on-chip]? off-chip Data cache [none, off-chip, on-chip]? off-chip Are I and D caches separate? yes I-cache total size in bytes? 8K to 256K I-cache associativity [direct-mapped, 2-set, 4-set, fully associative]? direct I-cache address block size in bytes (bytes per tag)? 4 I-cache transfer block size in bytes (bytes read on cache miss)? 16 to 128 I-cache index [virtual, physical]? physical I-cache tag [virtual, physical]? physical D-cache total size in bytes? 8K to 256K D-cache associativity [direct-mapped, 2-set, 4-set, fully associative]? direct D-cache writes [write-through, write-back]? write-through D-cache address block size in bytes (bytes per tag)? 4 D-cache transfer block size in bytes (bytes read on cache miss)? 16 to 128 D-cache index [virtual, physical]? physical D-cache tag [virtual, physical]? physical Is there a secondary cache? no > Branch Prediction What form of branch prediction is used, if any? none -- UUCP: {ames,decwrl,prls,pyramid}!mips!earl USPS: MIPS Computer Systems, 930 Arques Ave, Sunnyvale CA, 94086