pmontgom@euphemia.math.ucla.edu (Peter Montgomery) (10/03/90)
In article <1990Oct2.151644.1581@phri.nyu.edu> roy@phri.nyu.edu (Roy Smith) writes: > Are there actually any machines in which a compare-and-branch for >inequality is any faster or slower than a compare-and-branch for less-than? On the now obsolete CDC Cyber systems (ones complement) the compare and branch were combined into one instruction. Let Xi denote a 60-bit register. The major branch instructions were ZR Xi,address Branch if Xi == 0 (+0 or -0) NZ Xi,address Branch if Xi != 0 (neither +0 nor -0) PL Xi,address Branch if Xi >= 0 (look at sign bit) MI Xi,address Branch if Xi < 0 (look at sign bit) (four others tested out of range floating point values) The FORTRAN compiler often emitted shorter code for EQ and NE than for GT, GE, LT, LE. For example, if I and J are integer variables in registers X1 and X2, the object codes for IF(I.EQ.J) go to 10 and IF(I.GT.J) go to 10 might be IF (I.EQ.J) GO TO 10 IF (I.GT.J) GO TO 10 IX7 X1-X2 I-J IX7 X2-X1 J-I ZR X7,lab10 MX0 0 X0 = 0 IX7 X7+X0 J-I+0 MI X7,lab10 Because of the obscure case where I might be +0 and J be -0 (in which case the second IF should NOT branch), the compiler had to compute J-I+0 rather than J-I before the branch test. Sometimes compiler was smart enough to optimize this away, such as if I or J was known to be nonzero. Strangely, however, it was better to use GE, GT, LE, LT in relationals connected by .AND. or .OR., because ALL parts of the logical expression got evaluated (no short circuiting) and the ZR, NZ branches were not used on big expressions. For example IF (I1.EQ.0 .AND. I2.EQ.1) ... tested the sign of AND(NXOR(0-I,0+I), NXOR(1-I, I-1)) (NXOR = complemented exclusive OR) whereas IF (I1.GE.0 .AND. I2.GE.1) could test that of AND(I1+0, I2-1). I published an article in SIGPLAN Notices (December, 1978) about better code generation for these conditionals, but I never saw my suggestions adopted. -- Peter L. Montgomery pmontgom@MATH.UCLA.EDU Department of Mathematics, UCLA, Los Angeles, CA 90024-1555 If I spent as much time on my dissertation as I do reading news, I'd graduate.
seanf@sco.COM (Sean Fagan) (10/04/90)
In article <469@kaos.MATH.UCLA.EDU> pmontgom@euphemia.math.ucla.edu (Peter Montgomery) writes: > On the now obsolete CDC Cyber systems (ones complement) >the compare and branch were combined into one instruction. >Let Xi denote a 60-bit register. The major branch instructions were > > ZR Xi,address Branch if Xi == 0 (+0 or -0) > NZ Xi,address Branch if Xi != 0 (neither +0 nor -0) > PL Xi,address Branch if Xi >= 0 (look at sign bit) > MI Xi,address Branch if Xi < 0 (look at sign bit) > (four others tested out of range floating point values) On the other hand, if the compiler could restrict the values to 18 bits, then it could use EQ r1,r2,addr NE r1,r2,addr GT r1,r2,addr GE r1,r2,addr LT r1,r2,addr LE r1,r2,addr where r1 and r1 are one of the A or B registers. Note that since B0 was a hardwired 0, you also got ZR, NZ, PL, and MI thrown in for free. The FORTRAN compiler would normally use the B registers for looping and indexing; this allowed normal loops to have all the conditionals normally expected. -- -----------------+ Sean Eric Fagan | "Never knock on Death's door: ring the bell and seanf@sco.COM | run away! Death really hates that!" uunet!sco!seanf | -- Dr. Mike Stratford (Matt Frewer, "Doctor, Doctor") (408) 458-1422 | Any opinions expressed are my own, not my employers'.
seanf@sco.COM (Sean Fagan) (10/04/90)
In article <469@kaos.MATH.UCLA.EDU> pmontgom@euphemia.math.ucla.edu (Peter Montgomery) writes: > On the now obsolete CDC Cyber systems (ones complement) >the compare and branch were combined into one instruction. >Let Xi denote a 60-bit register. The major branch instructions were > > ZR Xi,address Branch if Xi == 0 (+0 or -0) > NZ Xi,address Branch if Xi != 0 (neither +0 nor -0) > PL Xi,address Branch if Xi >= 0 (look at sign bit) > MI Xi,address Branch if Xi < 0 (look at sign bit) > (four others tested out of range floating point values) On the other hand, if the compiler could restrict the values to 18 bits, then it could use EQ r1,r2,addr NE r1,r2,addr GT r1,r2,addr GE r1,r2,addr LT r1,r2,addr LE r1,r2,addr where r1 and r2 are one of the A or B registers. Note that since B0 was a hardwired 0, you also got ZR, NZ, PL, and MI thrown in for free. The FORTRAN compiler would normally use the B registers for looping and indexing; this allowed normal loops to have all the conditionals normally expected. -- -----------------+ Sean Eric Fagan | "Never knock on Death's door: ring the bell and seanf@sco.COM | run away! Death really hates that!" uunet!sco!seanf | -- Dr. Mike Stratford (Matt Frewer, "Doctor, Doctor") (408) 458-1422 | Any opinions expressed are my own, not my employers'.