[comp.arch] Final Program: ASPLOS-III

mfreeman@cascade.Stanford.EDU (Martin Freeman) (02/25/89)

		    Final Program for ASPLOS-III


		 Third International Conference on

		     Architectural Support for
	    Programming Languages and Operating Systems



		       Boston, Massachusetts
			  April 3-6, 1989


Sponsored by the ACM in cooperation with the IEEE Computer Society


Monday, April 3
---------------

8:00-9:00	Tutorial Registration
9:00-10:30	Tutorial I: Cache Consistency and Shared Memory Multiprocessors
		Jim Goodman, Univ. of Wisconsin
		Discussion of recent developments in memory design for
		    shared-memory multiprocessors.
10:30-11:00	Break
11:00-12:30	Tutorial I (continued)
12:30-1:30	Lunch
1:30-3:00	Tutorial II: Program Analysis and Restructuring for Concurrency
		Ron Cytron, IBM
		Examination of automatic restructuring of programs for
		    architectures that support various forms of concurrent
		    execution.
3:00-3:30	Break
3:30-5:00	Tutorial II (continued)
6:00-8:00	Registration: Reception  Cash Bar


Tuesday, April 4
----------------

8:00-9:00	Registration
9:00-10:00	Keynote Address
		Ken Thompson, AT&T Bell Labs
10:00-10:30	Break
10:30-12:00	Session I: Wide Instruction-Word Machines
		Chair: George Taylor, MIPS Computer Systems
		"Architecture and Compiler Tradeoffs for a Long Instruction
		    Word Microprocessor," Robert Cohn, Thomas Gross,
		    P.S. Tseng, Carnegie-Mellon University, Monica Lam,
		    Stanford University
		"Tradeoffs in Instruction Format Design for Horizontal
		    Architectures," Gurindar S. Sohi, S. Vajapeyam, University
		    of Wisconsin-Madison
		"Overlapped Loop Support in the Cydra-5," James C. Dehnert,
		    Peter Y.-T. Hsu, Joseph P. Bratt, Cydrome
12:00-1:30	Lunch
1:30-3:00	Session II: Synchronization
		Chair: Anant Agarwal, MIT
		"Architectural Support for Synchronous Task Communication,"
		    Forbes J. Burkowski, G.V. Cormack, G.D.P. Dueck, University
		    of Waterloo
		"The Fuzzy Barrier: A Mechanism for High Speed Synchronization
		    of Processors," Rajiv Gupta, North American Philips
		"Efficient Synchronization Primitives for Large-Scale
		    Cache-Coherent Multiprocessors," James R. Goodman, Mary K.
		    Vernon, Phil J. Woest, University of Wisconsin-Madison
3:00-3:30	Break
3:30-5:00	Session III: Support For Debugging
		Chair: Douglas Clark, DEC VAX Engineering
		"A Software Instruction Counter," John M. Mellor-Crummey,
		    Thomas J. LeBlanc, University of Rochester
		"Efficient Debugging Primitives for Multiprocessors," Ziya
		    Aral, Ilya Gertner, Greg Schaffer, Encore Computer
		"Sheaved Memory: Architectural Support for State Saving and
		    Restoration in Paged Systems," Mark E. Staknis,
		    Northeastern University
7:00-10:00	Banquet: New England Aquarium


Wednesday, April 5
------------------

8:30-10:00	Session IV: Operating System Issues
		Chair: Mike Powell, Sun Microsystems
		"Reference History, Page Size, and Migration Daemons in
		    Local/Remote Architectures," Mark A. Holliday, Duke
		"Translation Lookaside Buffer Consistency: A Software
		    Approach," David L. Black, Richard F. Rashid, David B.
		    Golub, Charles R. Hill, Robert V. Baron, Carnegie-Mellon
		    University
		"Failure Correction Techniques for Large Disk Arrays," Garth A.
		    Gibson, Lisa Hellerstein, Richard M. Karp, Randy H. Katz,
		    David A. Patterson, U. C. Berkeley
10:00-10:30	Break
10:30-12:00	Session V: Instruction Sets
		Chair: Dave Paterson, U. C. Berkeley
		"A Unified Vector/Scalar Floating-Point Architecture," Norman
		    Jouppi, Jonathan Bertoni, David Wall, Digital Equipment
		"Data Buffering: Run-time versus Compile-time Support,"
		    Hans Mulder, Delft University of Technology
		"An Analysis of 8086 Instruction Set Usage in MS-DOS Programs,"
		    Thomas L. Adams, Apple Computer, Richard E. Zimmerman, San
		    Francisco State University
12:00-1:30	Lunch
1:30-3:00	Session VI: Compiler/Language Issues
		Chair: Norman Jouppi, Digital Equipment
		"A Real-Time Support Processor for Ada Tasking," Joachin Roos,
		    University of Lund
		"The Runtime Environment for Screme, a Scheme Implementation
		    on the 88000," Steve R. Vegdahl, Uwe F. Pleban, Tektronix
		"Program Optimization for Instruction Caches," Scott McFarling,
		    Stanford University
3:00-3:30	Break
3:30-5:00	Session VII: Miscellaneous Topics
		Chair: Susan Eggers, Univ. of Washington
		"Using Registers to Optimize Cross-Domain Call Performance,"
		    Paul A. Karger, Digital Equipment
		"The Design of Nectar: A Network Backplane for Heterogeneous
		    Multicomputers," E.A. Arnould, F.J. Bitz, E.C. Cooper,
		    H.T. Kung, R.D. Sansom, P.A. Steenkiste, Carnegie-Mellon
		    University
		"A Message Driven OR-Parallel Machine," S.A. Delgado-Rannauro,
		    T.J. Reynolds, University of Essex
8:30-10:00	Panel Session: Instruction Level Parallelism  Whats Next?
		Organizer: Thomas Gross, Carnegie-Mellon University
		    Mitch Alsup, Motorola
		    Michael Blasgen, IBM Yorktown Heights
		    James Frankel, Thinking Machines
		    Norman Jouppi, Digital Equipment
		    David Papworth, Multiflow


Thursday, April 6
-----------------

8:30-10:00	Session VIII: Caching
		Chair: Faye Briggs, Sun Microsystems
		"Evaluating the Performance of Software Cache Coherence,"
		    Susan Owicki, Digital Equipment, Anant Agarwal, MIT
		"Analysis of Cache Invalidation Patterns in Multiprocessors,"
		    Wolf-Dietrich Weber, Anoop Gupta, Stanford University
		"The Effect of Sharing on the Cache and Bus Performance of
		    Parallel Programs," Susan J. Eggers, Univ. of Washington,
		    Randy H. Katz, U. C. Berkeley
10:00-10:30	Break
10:30-12:00	Session IX: Instruction Set Parallelism
		Chair: Jim Smith, Astronautics Corp. of America
		"Available Instruction-Level Parallelism for Superscalar and
		    Superpipelined Machines," Norman Jouppi, David Wall,
		    Digital Equipment
		"Micro-Optimization of Floating-Point Operations," W.J. Dally,
		    MIT
		"Limits on Multiple Instruction Issue," Michael D. Smith,
		    Mike Johnson, Mark A. Horowitz, Stanford University


Conference Chairs

	General		Joel Emer, Digital Equipment
	Program		John Hennessy, Stanford
	Treasurer	Dan Halbert, Digital Equipment
	Publicity	James Frankel, Thinking Machines
	Local Arrgmts.	Karen Sollins, MIT
	Registration	Toby Bloom, MIT


Program Committee

	John Hennessy, Stanford Univ. (chairman)
	Anant Agarwal, MIT
	Jean-Loup Baer, Univ. of Washington
	Faye Briggs, Sun Microsystems
	Douglas Clark, DEC VAX Engineering
	Jerry Huck, Hewlett-Packard
	Manolis Katevenis, Res. Ctr. of Crete, Greece
	Dave Patterson, U. C. Berkeley
	Mike Powell, Sun Microsystems
	Rick Rashid, CMU
	Jim Smith, Astronautics Corp. of America
	George Taylor, MIPS Computer Systems


Registration

Conference registration includes one copy of the proceedings, banquet,
lunches, breaks, etc.  Tutorial registration covers both tutorials and
includes one copy of notes for each tutorial, a lunch, and breaks.  Student
registration does not include the banquet.  Complete registration forms appear
in the ASPLOS-III advertisement in the January issues of either the
Communications of the ACM or of IEEE Computer Magazine.  The early
registration deadline is March 1.  For further information, contact Toby Bloom
at (617) 253-6023 or toby@lcs.mit.edu.


Conference Site

All technical sessions, lunches, and registration will be held at the Boston
Park Plaza Hotel, 50 Park Plaza at Arlington Street, Boston, Massachusetts.
An informal reception will be held from 6:00 PM to 8:00 PM on Monday evening
in conjunction with registration.  Participants and their guests are invited
to attend.  On Tuesday, the conference banquet will be held at the New England
Aquarium, located on Boston's waterfront.  The evening will afford the
participants ample opportunity to view the aquarium's many exhibits.  Free bus
transportation will be available to and from the hotel.  The cost of the
banquet is included in the registration fee.  Tickets for accompaning guests
may be reserved on the registration form; the cost is $45 per guest.


Transportation

Logan International Airport is approximately four miles from the Park Plaza
Hotel.  Individual taxi fare to the hotel is approximately eight dollars;
limousine or van service is available at approximately four dollars.  The
hotel is accessible from the Green Line of the subway (MBTA) system from the
Arlington stop.  Shuttle buses provide free transportation between the airline
terminals and the Airport stop on the Blue Line.  Transfer from the Blue to the
Green Line at the Government Center stop.  The subway fare is less than one
dollar.


Climate

The weather in Boston in April is generally pleasant with an average daily
temperature of 60 F.  A jacket is usually needed in the early morning and
evening, particularly along the waterfront.  Rain showers are always a
possibility in Boston at this time of year.  Casual attire is appropriate
throughout the conference, including at the aquarium.