dankg@typhoon.Berkeley.EDU (Dan KoGai) (06/11/90)
In article <16348@smunews.UUCP> leff@smu.seas.smu.edu (leff) writes: >From NYT, June 8, 1990, page C1 > >Hitachi Ltd, said today that it was the first to ... achieve: a working prototype >of a memory chip that can store more than 64 million bits of information. >...Most experts have predicted that the first 64-megabit chips would not be >ready until 1995. > >...comprises 140 million electronic devices, onto a surface that measures >9.74 millimeters by 20.28 millimeters. ... built with circuits ... 0.3 >micron wide. > >...etched with electron beams ... I read the same article, too. And surprised to find any other news sources reported that news I encountered: It wasn't mentioned in CNN's Science & Technology Week and its periodical news updates, not on San Francisco Chronicle (this one I'm not sure) and other massmedia. To bigger surprise, I coundn't find it on comp.arch, comp.lsi and other newsgroups. I want more info so I excerpted this artice to other newsgroup (I intended to do so but there was a post already). Follow-up is comp.arch so please give us more info/flame/et al. Dan Kogai (dankg@ocf.berkeley.edu)
lewine@dg.dg.com (Don Lewine) (06/11/90)
Here is the information that I have: Hitachi announced the development of a 64M bit DRAM [[Did not say anything about working parts.]] Operates on a single 1.5V power supply Access time is 50 ns. Power dissipation is 44mW. The device uses 0.3 micron technology Chips size is 9.74 x 20.28 mm. Memory cells are constructed with multi-layer capacitors. Hitachi expects to use this DRAM in protable OA equipment, note book size PC. (source: DENPA SHINBUN 6/8/90) --Don Lewine uunet!dg!lewine
khoult@bbn.com (Kent Hoult) (06/12/90)
In article <511@dg.dg.com> uunet!dg!lewine (Don Lewine) writes: >Here is the information that I have: > Hitachi announced the development of a 64M bit DRAM [[Did not say > anything about > working parts.]] The article I read yesterday on it said that they currently only have some sample DRAM cells working (a small number of bits). The sample cells were done with E-beam lithography. They don't expect to have a working 64M prototype for a year or two. The article was in the trade-rag that arrived yesterday (EE-times ?). Kent Hoult, BBN Communications Corp., Cambridge, MA khoult@bbn.com TEL: (617) 873-4385
thg@gmdzi.UUCP (Thomas Hagemann) (06/12/90)
From article <511@dg.dg.com>, by lewine@dg.dg.com (Don Lewine): > Here is the information that I have: > Hitachi announced the development of a 64M bit DRAM [[Did not say > anything about > working parts.]] > Operates on a single 1.5V power supply > Access time is 50 ns. > Power dissipation is 44mW. > The device uses 0.3 micron technology > Chips size is 9.74 x 20.28 mm. > Memory cells are constructed with multi-layer capacitors. > Hitachi expects to use this DRAM in protable OA equipment, note book > size PC. > > (source: DENPA SHINBUN 6/8/90) in addition, HITACHI plans to ship samples in 3 to 4 years, mass production will start in 1995. At the same time, MITSUBISHI ELECTRIC said it developed a new architecture for 64 MB DRAM-Chips with 40 ns access time, which is also applicable for next generation 256 MB DRAM's. -- Thomas Hagemann, German National Research Center for Computer Science (GMD) Schloss Birlinghoven, 5205 St. Augustin 1, West Germany thg@gmdzi.gmd.de ++49-2241-14-2079
raje@dolores.Stanford.EDU (Prasad Raje) (06/13/90)
About the 64Mbit DRAM: I havent read any of the trade rag announcements so I dont know if Hitachi made a separate announcement, but I was there at the VLSI Circuits Symposium in Hawaii where a paper on a 64Mb DRAM was presented. Here is the reference: Y.Nakagome et al, "A 1.5V Circuit Technology for 64Mb DRAMs", VLSI Circuits Symposium Digest, p 17, 1990. The paper mainly concentrated on circuit techniques (sense amp, word line driver, half Vcc voltage generator) for 1.5 V operation that will be required for 64Mbit DRAMs. They did have a chip microphotograph of the 64M DRAM but did not present measured data on this RAM. The access time of 50ns was obtained by circuit simulation. They probably do have working circuits for their new sense amps etc and did show some scope traces of wordline, and data out waveforms. Some details on the technology for those who do not have access to the reference (most libraries may not have the Digest yet) Organization: 16Mx4 Techonology: 0.3um P substrate, triple well CMOS Oxide thickness: 65A Gate Length: 0.5um (N), 0.6um (P) Cell: Stacked Capacitor cell, 44fF Ccell 0.8 um x 1.6 um = 1.28 um^2 Chip size: 9.74 mm x 20.28 mm = 197.5 mm^2 Power Supply: 1.5 or 3.3V external, 1.5V internal Access time: 50ns Enjoy Prasad
hcobb@walt.cc.utexas.edu (Henry J. Cobb) (06/13/90)
The mistakes of the present carried to the technology of the future. Eight MegaBytes stacked behind a 50ns nibble-wide port is almost a second for a blind burst read. A 24-bit wide "full color" bitplane built from these suckers only gives a 500x800 display at 50Hz. (thou you could have 40 such screens packed in the chips). Just give me a port with 21 bits of address and 32 bits of data for direct connection to my CPU. If I need more than 8MB of RAM, I'll probably need more than one processor anyway. Henry J. Cobb hcobb@ccwf.cc.utexas.edu Tyrant of the SFB-tactics E-Mailing list.
jonah@db.toronto.edu (Jeff Lee) (06/13/90)
hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes: > Just give me a port with 21 bits of address and 32 bits of >data for direct connection to my CPU. If I need more than 8MB of RAM, >I'll probably need more than one processor anyway. A 20MHz processor plus a dedicated 8MB 50ns memory (i.e. no cache) -- or a board full of these -- would seem to be quite useful for some applications. On the other hand, a 4-bit wide memory means you need 64MB (8 chips) to get a 32-bit wide memory and 128MB (16 chips) to make a 64-bit wide memory -- which is more than you may want dedicate as "local" memory for a smart controller of some sort. Can anyone with a hardware design background say what the problem is with wider memory chips (BESIDES having to change the packaging/pinout of the memory chips). j.
rick@ameristar (Rick Spanbauer) (06/13/90)
In article <31499@ut-emx.UUCP> hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes: > The mistakes of the present carried to the technology of the future. > Eight MegaBytes stacked behind a 50ns nibble-wide port is >almost a second for a blind burst read. > A 24-bit wide "full color" bitplane built from these suckers >only gives a 500x800 display at 50Hz. (thou you could have 40 such >screens packed in the chips). > Just give me a port with 21 bits of address and 32 bits of >data for direct connection to my CPU. If I need more than 8MB of RAM, >I'll probably need more than one processor anyway. > > Henry J. Cobb hcobb@ccwf.cc.utexas.edu Well said. There is light at the end of the tunnel though. It seems many/most of the majors are looking to widen their memory ports, eg some have 64kx16 rams on the horizon, x8 vrams now, etc. TI is starting a line of ssop packaged x16 buffer/register parts. Now all we need is a packaging technology to contain all those 128+ bit busses, eg multichip modules anyone? ;-) Of course a 32 bit port into vram isn't going to make you a happy camper either if you want your hdtv resolution (1920x1080) screen to update at a reasonable rate. Me? I want at least 256 bits into my frame buffer.. Rick Spanbauer Ameristar
dhinds@portia.Stanford.EDU (David Hinds) (06/13/90)
In article <31499@ut-emx.UUCP> hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes: > > The mistakes of the present carried to the technology of the future. > Eight MegaBytes stacked behind a 50ns nibble-wide port is >almost a second for a blind burst read. > A 24-bit wide "full color" bitplane built from these suckers >only gives a 500x800 display at 50Hz. (thou you could have 40 such >screens packed in the chips). Gee, I guess that progress in the semiconducter industry isn't always defined by who can make the biggest, fastest, most colorful frame buffer. > Just give me a port with 21 bits of address and 32 bits of >data for direct connection to my CPU. If I need more than 8MB of RAM, >I'll probably need more than one processor anyway. One would assume that the intended market for this device is not "[your] CPU" :-) There seem to be a number of single-processor systems around that CAN make reasonable use of more than 8MB of memory. It isn't clear to me why DRAM's are nearly always bit-wide or nibble- wide, besides tradition. Compatibility doesn't seem to be an issue for this chip. Is it possible that error correction circuitry can somehow be more efficient this way? I would expect that this chip has a significant amount of space devoted to error correction. Alternatively, (more likely?) the intention is to keep the markets for successive generations of chips from overlapping too much. To move up to the next higher density, you are forced to buy a lot more memory this way. -David Hinds dhinds@popserver.stanford.edu
daveh@cbmvax.commodore.com (Dave Haynie) (06/14/90)
In article <90Jun12.183151edt.2787@ois.db.toronto.edu> jonah@db.toronto.edu (Jeff Lee) writes: >hcobb@walt.cc.utexas.edu (Henry J. Cobb) writes: >Can anyone with a hardware design background say what the problem is >with wider memory chips (BESIDES having to change the packaging/pinout >of the memory chips). I think the issue so far has just been density. Before the 1 Meg density parts came along, you rarely found a DRAM that wasn't a simple 1 bit part. Certainly there were 64k x 4 parts in the 256K density, but they weren't very popular. With the 1 Meg and 4 Meg parts, the 4 bit packages are more popular, since that amounts to a reasonable chunk of memory -- 512K on a 16 bit bus or 1 Meg on a 32 bit bus with 1 Meg density parts. You probably don't want less for most applications, and going to an 8 or 16 bit package would increase board space for the same amount of memory. There are already specifications for 8 bit DRAMs, and I wouldn't be surprised to see these become popular when 16M DRAM gets reasonable. The other issue is of course the standard packaging; I can build a board today for 256k x 4 parts which can easily support the 1 Meg x 4 parts, since they use compatible packages. This is much less an issue if you're using memory modules, since the PCB of the module sorts out the actual packaging issues for you. But you're not going to have 4 or 16 Meg x 4 parts in a compatible package anyway, so I imagine a new basic DRAM part size will become the standard one when these parts are out in force. >j. -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "I have been given the freedom to do as I see fit" -REM
jesup@cbmvax.commodore.com (Randell Jesup) (06/14/90)
In article <1990Jun11.032747.15462@agate.berkeley.edu> dankg@typhoon.Berkeley.EDU (Dan KoGai) writes: >In article <16348@smunews.UUCP> leff@smu.seas.smu.edu (leff) writes: >>From NYT, June 8, 1990, page C1 >> >>Hitachi Ltd, said today that it was the first to ... achieve: a working prototype >>of a memory chip that can store more than 64 million bits of information. >>...Most experts have predicted that the first 64-megabit chips would not be >>ready until 1995. Note: according the EETimes, it is NOT a working prototype. It is 18 months or 2 years from being a working prototype according to Hitachi. -- Randell Jesup, Keeper of AmigaDos, Commodore Engineering. {uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com BIX: rjesup Common phrase heard at Amiga Devcon '89: "It's in there!"
davidb@braa.inmos.co.uk (David Boreham) (06/14/90)
In article <90Jun12.183151edt.2787@ois.db.toronto.edu> jonah@db.toronto.edu (Jeff Lee) writes: > >A 20MHz processor plus a dedicated 8MB 50ns memory (i.e. no cache) -- >or a board full of these -- would seem to be quite useful for some >applications. On the other hand, a 4-bit wide memory means you need Hmm, by the time these little beauties hit the market 20MHz will be almost DC :) and probably only used for very low power applications. 50ns is about adequate on today's fast CMOS processors. >Can anyone with a hardware design background say what the problem is >with wider memory chips (BESIDES having to change the packaging/pinout >of the memory chips). Packaging and pinout is no problem. Finding the power to drive all the output pins fast is a bit of a problem. However, don't expect 64Mbit DRAMs to hit the market looking anything like today's 1/4Mbit parts. If they do then we really will be in trouble. David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos.com!davidb +44 454 616616 ex 547 | Internet: davidb@inmos.com
suhler@ibm.com (Paul Suhler) (06/14/90)
David Hinds (dhinds@popserver.stanford.edu) writes: > It isn't clear to me why DRAM's are nearly always bit-wide or nibble- >wide, besides tradition. Compatibility doesn't seem to be an issue for >this chip. Is it possible that error correction circuitry can somehow >be more efficient this way? [...] The reason to prefer bit-wide RAMs is that if a single chip fails, then ECC can still correct the error. If two or more bits go at once, then it can't. Paul Suhler Hybrid Dataflow Systems
gillies@m.cs.uiuc.edu (06/16/90)
Actually, a 2-bit DRAM is just as minimal as a 1-bit DRAM, w.r.t. pin count. Has anyone ever sold a 2-bit DRAM part?
lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) (06/17/90)
In article <1990Jun13.051630.6829@ameristar> rick@ameristar (Rick Spanbauer) writes: >Now all we need is a >packaging technology to contain all those 128+ bit busses, eg multichip >modules anyone? ;-) Of course a 32 bit port into vram isn't going to >make you a happy camper either if you want your hdtv resolution (1920x1080) >screen to update at a reasonable rate. Me? I want at least 256 bits into >my frame buffer.. As I've said before in this forum, I see at least nine candidate technologies that will allow cm^2 chips to have 1,000+ pins. (The nine are: 1) flip chip 2) insetting to planarize with substrate 3) multilayer TAB 4) mechanically stacked active regions 5) metallizing a beveled chip edge 6) trenched cantilevers 7) chip vias 8) wafer scale 9) [speculative!] onchip optical elements. If anyone has more [not the Cray-3 technology], I'd appreciate mail. ) Most of these imply or require that you are communicating with something nearby, and in a very controlled environment. Even then, power is going to be an issue, with multilayer TAB probably being the worst. Such a superchip will initially be expensive, just as 40-pin DIPs were once expensive. (The 68000, in its 64 pin DIP, was awesome.) So, the superchip will probably hold a CPU or four, with the pins for primary cache(s) <===> secondary cache. It won't necessarily be a single 1024-signal bus: it may be several buses, and they may be double railed, or unidirectional, or both. Note that clock rates should be past 100 MHz ( ie 10 ns ) by then: it is the agonized search for nanoseconds will drive us to this packaging. The MIPS RC6280 (R6000 ECL box) has an 8 word primary-I-line and a 2 word primary-D-line, i.e. a logical width of 320 bits. That seems consistent with the superchip. The "Micro 2000" suggested by Intel in the Oct89 IEEE Spectrum is described as 250 MHz, one square inch, and with a 2 MB onchip secondary cache. That would have room for 2K+ pins, again consistent with the 32 word (1024 bit) line size of the RC6280 secondary cache. As for frame buffers ... Sony has a 2K x 2K color monitor: 72 Hz is a standard: that gives a pixel rate of 302 MHz, or 24 bits every 3.3 nano. Assuming VRAM with 50 MHz shift rates (twice what MegaScan uses), the refresh alone has to be 144 bits wide. I presume that the non-serial VRAM port needs a similar bandwidth? -- Don D.C.Lindsay leaving CMU .. make me an offer!