josh@klaatu.rutgers.edu (J Storrs Hall) (01/09/90)
I'd like people's reactions to these predictions on microprocessor
technology by the turn of the century. They are intended to
indicate something on the order of "state of the art but commercially
available", use the "1990" column to guess what level I'm getting at.
("pins" is high but intended to indicate more state of the art;
I really just guessed at memory speeds ca. 1980.)
what 1980 1990 extrapolation 2000
processor
pins 64 256 x4 1k
clock 8MHz 32MHz x4 128MHz
"Devices" 50k 1M x20 20M
mips 1 12 x12 144
memory(dram)
bits/chip 16k 1M x64 64M
speed 240ns 80ns /4 20ns
--JoSHcasey@gauss.llnl.gov (Casey Leedom) (01/10/90)
| From: josh@klaatu.rutgers.edu (J Storrs Hall) | | what 1980 1990 extrapolation 2000 | processor | pins 64 256 x4 1k | clock 8MHz 32MHz x4 128MHz | "Devices" 50k 1M x20 20M | mips 1 12 x12 144 | memory(dram) | bits/chip 16k 1M x64 64M | speed 240ns 80ns /4 20ns "pins" and "clock" are the only ones I have an argument with. The mechanical insertion force necessary for a 1K pin chip would be prohibitive if no other considerations came into play. I think we're much more likely to see surface mount modules containing CPU, floating point, memory management, primary- and secondary- cache, high speed bus, memory and I/O access. The advanced mounting technology will take advantage of both sides of the module board(s) and be very small and dense. The fancier modules will have provision for multiple busses and paths to memory and I/O. On the clock issue I just think you're way too conservative. I expect to see 128MHz within a year to a year and a half. What the clock speeds on KMs will be in 2000 I couldn't guess, but they will be faster than 128MHz. Casey
hascall@cs.iastate.edu (John Hascall) (01/10/90)
In article <???> josh@klaatu.rutgers.edu (J Storrs Hall) writes: }I'd like people's reactions to these predictions on microprocessor }technology by the turn of the century... }what 1980 1990 extrapolation 2000 }processor }pins 64 256 x4 1k }clock 8MHz 32MHz x4 128MHz }"Devices" 50k 1M x20 20M }mips 1 12 x12 144 }memory(dram) }bits/chip 16k 1M x64 64M }speed 240ns 80ns /4 20ns ^ | +-- Can we assume a linear relationship??? Perhaps someone could add in a few more data points between '80 and '90. John Hascall / ISU Comp Ctr / Ames, IA
dgr@hpfcso.HP.COM (Dave Roberts) (01/10/90)
Josh writes: >I'd like people's reactions to these predictions on microprocessor >technology by the turn of the century. They are intended to >indicate something on the order of "state of the art but commercially >available", use the "1990" column to guess what level I'm getting at. >("pins" is high but intended to indicate more state of the art; >I really just guessed at memory speeds ca. 1980.) > >what 1980 1990 extrapolation 2000 >processor >pins 64 256 x4 1k >clock 8MHz 32MHz x4 128MHz >"Devices" 50k 1M x20 20M >mips 1 12 x12 144 >memory(dram) >bits/chip 16k 1M x64 64M >speed 240ns 80ns /4 20ns > >--JoSH >---------- Well, I've got to say, clock seems a bit low by the year 2000, as number of pins seems high. I doubt that bus widths will grow too much internally to processors (although external bus widths probably will). That will tend to limit the pin expansion as will packaging limitations. There will have to be some *big* advances in packaging to support that rate of growth. Clock speed should definitely (at current growth rates) exceed that (assuming state of the art). The other stuff I could believe (of course MIPS would scale with processor speed, as would the "speed" parameter). -- Dave
ran@cs.utah.edu (Ran Ginosar) (01/10/90)
I have seen published predictions by Intel similar to Josh's numbers, except that they plan on 100M transistors per chip, not just 20M. -- Dr. Ran Ginosar ran@cs.utah.edu Computer Science Department, University of Utah Salt Lake City, UT 84112. Phone: 801-581-7705, fax 801-581-5843.