kum@sccmts.Sun.COM (Kumar Venkatasubramaniam) (09/08/89)
I am looking for information on the use of parity for error detection in large systems. Apart from the obvious use in detecting errors in memory data and errors in long buses susceptible to noise, does anyone know of parity being carried through the internal paths of a processor? The major microprocessors (that I know of) available in the market deal with parity only at the bus interface. Are there large systems (mainframes, supercomputers) that perform additional parity checks internally and under what conditions? Do military and space applications impose any such requirements? I would appreciate any information on this subject. Kumar Venkat Sun Microsystems kum@Corp.sun.com
barry@PRC.Unisys.COM (Barry Traylor) (09/08/89)
In article <124311@sun.Eng.Sun.COM> kum@sccmts.Sun.COM (Kumar Venkatasubramaniam) writes: > ... >Are there large systems (mainframes, supercomputers) that >perform additional parity checks internally and under what >conditions? ... The Unisys large A Series (A12/15/17) uses either parity or mod 3 residue on not only data paths, but the results of alu operations. Very few data paths are not protected. Residue is used wherever possible and practical. In addition to the processor error checking, the processor will report a "proc internal" error to software, which will attempt a single retry of the instruction that discovered the error. Barry Traylor Unisys A Series Engineering
blarson@basil.usc.edu (bob larson) (09/08/89)
In article <124311@sun.Eng.Sun.COM> kum@sccmts.Sun.COM (Kumar Venkatasubramaniam) writes: >Apart from the obvious use in >detecting errors in memory data and errors in long buses >susceptible to noise, does anyone know of parity being >carried through the internal paths of a processor? Prime does use parity on internal busses. Cache parity errors on prime machines with write-through cache cause the data to be re-read from main memory. (Main memory is ECC, of course.) Uncorrectable main memory errors will do a page fault if the page is on disk. (This refers to recent members of the 50 series, not ancient history or machines from other companies sold under the Prime label.) -- Bob Larson Arpa: blarson@basil.usc.edu Uucp: {uunet,cit-vax}!usc!basil!blarson Prime mailing list: info-prime-request%ais1@usc.edu usc!ais1!info-prime-request
roy@phri.UUCP (Roy Smith) (09/08/89)
In <124311@sun.Eng.Sun.COM> kum@sccmts.Sun.COM (Kumar Venkatasubramaniam): > does anyone know of parity being carried through the internal paths of a > processor? The AT&T 3B20D does. This was (is?) the machine which drives the 5ESS phone switches. Every internal data path is parity checked or duplicated and compared in places where parity is impractical, like the ALU (I don't know of any way to calculate the parity of, for example, an integer multiply). There was a special issue of BSTJ on it about 5-10 years ago. -- Roy Smith, Public Health Research Institute 455 First Avenue, New York, NY 10016 {att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu "The connector is the network"
pdbain@bmers58.UUCP (Peter Bain) (09/08/89)
In article <124311@sun.Eng.Sun.COM> kum@sccmts.Sun.COM (Kumar Venkatasubramaniam) writes: > > >I am looking for information on the use of parity for error >detection in large systems. Apart from the obvious use in >detecting errors in memory data and errors in long buses >susceptible to noise, does anyone know of parity being >carried through the internal paths of a processor? >Kumar Venkat >Sun Microsystems >kum@Corp.sun.com DOC_TYPE journal-article TITLE DPS 88 Error Detection and Recovery Features and Mechanisms AUTHOR G.C. Edgington JOURNAL Scientific Honeyweller VOLUME 5 NUMBER 1 YEAR March 1984 PAGES 8-10 KEYWORDS error recovery detection parity residue
baum@Apple.COM (Allen J. Baum) (09/09/89)
[] >In article <124311@sun.Eng.Sun.COM> kum@sccmts.Sun.COM (Kumar Venkatasubramaniam) writes: > >I am looking for information on the use of parity for error >detection in large systems. Apart from the obvious use in >detecting errors in memory data and errors in long buses >susceptible to noise, does anyone know of parity being >carried through the internal paths of a processor? I think that most of the large IBM mainframes have parity on registers and data-paths, but I dont have strong information. Carrying parity through the ALU is a bit tougher, expecially for shifters. There was a set of bit-slice ECL parts made by Motorola (originally designed for Univac, I think), that had such things as "parity of internal carries", which could be used to do just that. [ P(a) ^ P(b) ^ P(carries) = P(a+b) ] Parity of logic operations is just a little trickier- you need to generate the operation, and its 'deMorgan equivalent', so P(a) ^ P(b) = P(a&b) ^ P(a|b) -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum
mash@mips.COM (John Mashey) (09/09/89)
In article <34595@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes: >[] ..... >I think that most of the large IBM mainframes have parity on registers and >data-paths, but I dont have strong information. Carrying parity through the ........ We don't do them on internal datapaths. RX000 CPUs do generate and check parity for the caches, and they call a parity error a cache-miss, but then set a CPU staus register bit that can be checked occasionally by the kernel to see if something is failing. There are also modes in the cache control to: isolate the caches write data with bad parity into the cache read the cache, and get a parity-right versus parity-wrong bit, so you can test the parity circuits. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) (09/12/89)
>The major microprocessors (that I know of) available in the market >deal with parity only at the bus interface. Are there large systems >(mainframes, supercomputers) that perform additional parity checks >internally and under what conditions? While working for a minicomputer company, I heard that the major difference between minicomputers and microcomputers was that minis did error detection (and occasionally correction) on major functional data paths, not just the bus, and micros didn't. I believe that many minis have internal parity checks - in particular Gould PN and NPs. See the appropriate technical manuals. Academic ref: In the Proceedings of the 8th Symposium on Computer Arithmetic, 1987, Robertson has a paper on extending parity to check for correct functioning of ALUs, etc. -- eg. parity(sum)=sum(parity). Coincidentally, I am doing a literature survey of computer arithmetic under Robertson - I can ask him for further refs if you want. -- Andy "Krazy" Glew, Motorola MCD, aglew@urbana.mcd.mot.com 1101 E. University, Urbana, IL 61801, USA. {uunet!,}uiucuxc!udc!aglew My opinions are my own; I indicate my company only so that the reader may account for any possible bias I may have towards our products.
henry@utzoo.uucp (Henry Spencer) (09/14/89)
In article <AGLEW.89Sep11230245@chant.urbana.mcd.mot.com> aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) writes: >While working for a minicomputer company, I heard that the major >difference between minicomputers and microcomputers was that minis did >error detection (and occasionally correction) on major functional data >paths, not just the bus, and micros didn't... This is, at the very least, a revisionist definition of "minicomputer". None of the major minis -- back in the days when the distinction was clear -- did such detection on either the bus or the internal data paths. If you were lucky, they did it on their memory boards, but even that was by no means universal. -- V7 /bin/mail source: 554 lines.| Henry Spencer at U of Toronto Zoology 1989 X.400 specs: 2200+ pages. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
bruce@tolerant.UUCP (Bruce Hochuli) (09/15/89)
In article <AGLEW.89Sep11230245@chant.urbana.mcd.mot.com> aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) writes: >>The major microprocessors (that I know of) available in the market >>deal with parity only at the bus interface. Are there large systems >>(mainframes, supercomputers) that perform additional parity checks >>internally and under what conditions? > >While working for a minicomputer company, I heard that the major >difference between minicomputers and microcomputers was that minis did >error detection (and occasionally correction) on major functional data >paths, not just the bus, and micros didn't. I believe that many >minis have internal parity checks - in particular Gould PN and NPs. >See the appropriate technical manuals. > The split that I remember was between mainframes and minicomputers where the mainframes had oodles of error checking and the minis had ECC on the memory, parity on the main bus, and not much more. I was involved in one project where the end product was an IBM 370 clone and the project personnel was about 50/50 mainframe/ minicomputer people. The discussions about internal error checking were very spirited (read screaming, shrieking fights lacking only knives and guns). The minicomputer people won and we did it mini style (just for the record, I was in the losing camp) with minimal error detection.