[comp.arch] Harvard RISC

brooks@lll-crg.llnl.gov (Eugene D. Brooks III) (02/26/88)

I read some "hype" concerning the Motorola RISC chip set
in Electronics today.  I would like to find a reference
to the "Harvard RISC" architecture.  Anyone know of
a suitable paper?

hs0l+@andrew.cmu.edu (Hugh Brinkley Sprunt) (02/28/88)

> I read some "hype" concerning the Motorola RISC chip set
> in Electronics today.  I would like to find a reference
> to the "Harvard RISC" architecture.  Anyone know of
> a suitable paper?

    I think what is being referred to in the Electronics is
    "Harvard" style machines (as opposed to "Princeton"
    style).  A Harvard class machine has separate data
    and instruction buses (or in this case, separate caches
    for instructions and data).  A Princeton class machine
    has only one bus for both instructions and data.

    Does anyone know why and when these classifications
    developed?

				Brink