trb@stag.UUCP ( Todd Burkey ) (06/14/89)
I am looking for information on a FPU chip set from a company I think is called BIT. It is rated at 50MFLOP, is hopefully 32 bit, and I think it is ECL based. Any information would be appreciated, including pricing, specs, and availability. Also, I would be interested in hearing if that 50MFLOP rating is peak or effective w/load and store of data to memory. Thanks, -Todd Burkey pwcs!stag!trb
mslater@cup.portal.com (Michael Z Slater) (06/19/89)
> Now that there is an 80 MHz sparc out, how will this affect Prisma's chip?
Prisma is not developing a chip - they are developing a system, with a
cpu built out of many chips. And they are targeting several times the
performance level of the BIT SPARC. What the will actually achieve is
another question.
Michael Slater, Microprocessor Report mslater@cup.portal.commdeale@mira.acs.calpoly.edu (Myron Deale) (06/20/89)
In article <871@stag.UUCP> trb@stag.UUCP ( Todd Burkey ) writes: >I am looking for information on a FPU chip set from a company I think >is called BIT. It is rated at 50MFLOP, is hopefully 32 bit, and I think >it is ECL based. Any information would be appreciated, including pricing, >specs, and availability. Also, I would be interested in hearing if that >50MFLOP rating is peak or effective w/load and store of data to memory. > Thanks, > -Todd Burkey > pwcs!stag!trb Hello, Bipolar Integrated Technology, Inc. (BIT) located in Beaverton, OR, makes the B3110/B3120 (ECL, there's also a TTL version) Floating Point Chip Set (the "preliminary" data sheets say Sept/87). Peak perfor- mances are listed as: "22 MFLOPS double precision multiply data rate, 40 MFLOPS double precision ALU data rate, 100 MIPS integer data rate." More recently, they have announced (EDN news, EE Times, etc.) the first ECL implementation of Sun's SPARC. The "integer unit operates at 80 MHz and provides 65 MIPS (average CPI of 1.2). The integer unit and its associatd floating-point subsystem together offer 14M-FLOPS perfor- mance." (double-precision Linpack). [EDN news, 6/15/89, p.14] The five other chips that comprise the fp subsytem supposedly use upgraded B3110/20 chips. It's a bit pricy, but what do you expect, it's ECL. Reads like a good implementation of SPARC has shown up. One thing I am troubled by is the cache memory set-up. I am completely un-bothered by the need for a second-level cache. However, I am worried that the primary level (closest to the CPU) has its architecture pre-defined by the chip builders, ie. I don't get to tweak the design of the cache (if I ever decide to work with this stuff). "Say it isn't so." Myron // mdeale@cosmos.acs.calpoly.edu
mslater@cup.portal.com (Michael Z Slater) (06/21/89)
> Reads like a good implementation of SPARC has shown up. One thing I am >troubled by is the cache memory set-up. I am completely un-bothered by >the need for a second-level cache. However, I am worried that the >primary level (closest to the CPU) has its architecture pre-defined by >the chip builders, ie. I don't get to tweak the design of the cache (if >I ever decide to work with this stuff). "Say it isn't so." It isn't so. BIT provides no cache support, giving you the freedom to do whatever you want for the first-level cache. On the other hand, this gives you the obligation to figure out how to build a 12-ns cache system. The only cache limitation is that the IU provides separate address lines for the cache that are clocked earlier in the cycle, and these lines support a maximum of 512 Kbytes of cache. Given the cost of the 8-ns RAMs you need to build this cache, that size limitation shouldn't be much of a problem. BIT admits that the system designer will have to build a few ASICs to make the cache and MMU. It will be interesting to see how the MIPS ECL design handles this. Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677
grunwald@flute.cs.uiuc.edu (Dirk Grunwald) (07/22/89)
Could this perhaps refer to the recent MECL implementation of the SPARC architecture, as recently reported in (I think) Electronic Design? Now that there's an 80Mhz (I think it was) SPARC out, how is the Prisma chip going to find a market niche? Will ted marry alice? And about about those aliens? God I love RISC. -- Dirk Grunwald -- Univ. of Illinois (grunwald@flute.cs.uiuc.edu)
mslater@cup.portal.com (Michael Z Slater) (07/23/89)
> ECL FPU from BIT
BIT recently introduced their ECL SPARC chip set, which uses some ECL
FPU components. The SPARC IU and floating-point coprocessor are new
chips; they work with two FP register file chips, a FP ALU, and an
FP multiplier chip, which have been around for a couple years and are
general-purpose. I don't know what the FP chips sell for separately,
but the full SPARC chip set is $3300 in 100s; the IU alone is $850. The SPARC
set is rated at 40 MFLOPS peak, 14 MFLOPS for compiled double-precision
Linpack. Integer performance is stated as 50 to 65 MIPS; clock rate
is 80 MHz. Samples are now available, and production is scheduled for
early '90.
Michael Slater, Microprocessor Report mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677khb%chiba@Sun.COM (Keith Bierman - SPD Languages Marketing -- MTS) (08/03/89)
In article <GRUNWALD.89Jun17210544@flute.cs.uiuc.edu> grunwald@flute.cs.uiuc.edu writes: > >Now that there's an 80Mhz (I think it was) SPARC out, how is the Prisma >chip going to find a market niche? Prisma doesn't make chips. They build systems. As I understand it, it will be a 4nsec (i.e. 250 native MIPS) IU, 100mflops (peak or sustained ?) FPU up to 32 channel controllers, and other associated goodies. So, if they can build and ship in sometime in the first half of next year, it should give E&S, Convex, Alliant and Multiflow a run for their money. > >Will ted marry alice? No. >And about about those aliens? Probably win the pennant race. >God I love RISC. :> Keith H. Bierman |*My thoughts are my own. Only my work belongs to Sun* It's Not My Fault | Marketing Technical Specialist ! kbierman@sun.com I Voted for Bill & | Languages and Performance Tools. Opus (* strange as it may seem, I do more engineering now *)
mslater@cup.portal.com (Michael Z Slater) (08/03/89)
>Could this perhaps refer to the recent MECL implementation of the SPARC >architecture, as recently reported in (I think) Electronic Design? > >Now that there's an 80Mhz (I think it was) SPARC out, how is the Prisma >chip going to find a market niche? "The Prisma chip" is not a chip by a long shot. Prisma is building a GaAs minisupercomputer, whose cpu will be hundreds (possibly thousands) of chips. It happens to use the SPARC architecture (for software availability), but is in no sense a SPARC chip. GaAs isn't there yet; maybe someone else can give an estimate of how long it will be before GaAs chips of several hundred thousands transistors are practical. Prisma's systems, by the way, will be priced in hundreds of thousands of dollars. Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677