lindsay@gandalf.cs.cmu.edu (Donald Lindsay) (09/24/90)
>Subject: Re: Discontintuiy
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Sorry about that. Gee, I hate noisy phone lines.
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Don D.C.Lindsaylindsay@gandalf.cs.cmu.edu (Donald Lindsay) (09/26/90)
In article <1990Sep24.041001.24220@nlm.nih.gov> states@tech.NLM.NIH.GOV (David States) writes: >In article <10550@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: >>..high speed is best served by having a fast primary cache, and a >>slightly slower secondary cache. >>Notice that throughput just isn't that sensitive to the size of the >>primary cache. >Isn't the key here the use of a secondary cache which is only slightly >slower? Yes. Luckily, it's not an arbitrary assumption. If you look up a vendor's family of hot SRAMs, you'll find that using a 4X larger SRAM chip adds only a few nanoseconds to the access time. As a cache design is enlarged, it crosses over the point where the access can't be done in one clock. But it isn't difficult for the big cache to work in two clocks. So, a fault-in-primary/hit-in-secondary doesn't really cost much time. That's why it's not important to have a big primary. Of course, if the primary is on-chip, and the secondary isn't - or if the secondary is massive, or "cost effective" - then the secondary might take, say, three clocks. Still not too bad... It is usually assumed that both caches are cycled at once. If the primary hits, then the secondary's access is cancelled. This scheme improves the effective speed of the secondary. It has a downside: if the primary is onchip, then we're cycling the power-hungry pins on every clock, instead of 1/N'th of the time. Plus, the cache control - complicated anyway - has to cope with even more fun possibilities. (For example, the secondary may be busy completing a refill, or doing a snoop. Do you even want to think about multiple outstanding requests?) >Might not a big chip >which didn't require secondary cache be an overall win on lower end systems? It's possible, but low-end systems can also be built other ways. For example, by running the same chip at a lower clock rate, one can build the secondary cache out of denser SRAM. -- Don D.C.Lindsay