[comp.arch] RISC speed madness

grunwald@m.cs.uiuc.edu (10/04/88)

You don't need much 40ns RAM. You can have a multi-level cache
stagging to cheaper RAM, i.e. 32Kb of 40ns cache for 1Mb of 80ns cache
for 32Mb of 200ns ram.

Recent papers (last sigarch?) show that this is a very reasonable thing
to do.